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arm64: Add TCR register masks
These will be used by bhyve to implement page table walking. Sponsored by: Arm Ltd
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@ -2141,6 +2141,7 @@
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#define TCR_IPS_44BIT (4UL << TCR_IPS_SHIFT)
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#define TCR_IPS_48BIT (5UL << TCR_IPS_SHIFT)
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#define TCR_TG1_SHIFT 30
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#define TCR_TG1_MASK (3UL << TCR_TG1_SHIFT)
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#define TCR_TG1_16K (1UL << TCR_TG1_SHIFT)
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#define TCR_TG1_4K (2UL << TCR_TG1_SHIFT)
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#define TCR_TG1_64K (3UL << TCR_TG1_SHIFT)
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@ -2155,8 +2156,10 @@
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#define TCR_A1_SHIFT 22
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#define TCR_A1 (0x1UL << TCR_A1_SHIFT)
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#define TCR_T1SZ_SHIFT 16
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#define TCR_T1SZ_MASK (0x3fUL << TCR_T1SZ_SHIFT)
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#define TCR_T1SZ(x) ((x) << TCR_T1SZ_SHIFT)
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#define TCR_TG0_SHIFT 14
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#define TCR_TG0_MASK (3UL << TCR_TG0_SHIFT)
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#define TCR_TG0_4K (0UL << TCR_TG0_SHIFT)
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#define TCR_TG0_64K (1UL << TCR_TG0_SHIFT)
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#define TCR_TG0_16K (2UL << TCR_TG0_SHIFT)
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@ -2170,7 +2173,7 @@
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#define TCR_EPD0 (1UL << TCR_EPD0_SHIFT)
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/* Bit 6 is reserved */
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#define TCR_T0SZ_SHIFT 0
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#define TCR_T0SZ_MASK 0x3f
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#define TCR_T0SZ_MASK (0x3fUL << TCR_T0SZ_SHIFT)
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#define TCR_T0SZ(x) ((x) << TCR_T0SZ_SHIFT)
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#define TCR_TxSZ(x) (TCR_T1SZ(x) | TCR_T0SZ(x))
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