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hme(4): Remove as previous announced
The hme (Happy Meal Ethernet) driver was the onboard NIC in most supported sparc64 platforms. A few PCI NICs do exist, but we have seen no evidence of use on non-sparc systems. Reviewed by: imp, emaste, bcr Sponsored by: DARPA
This commit is contained in:
Brooks Davis
parent
f7cc0eae7e
commit
9ee99cec1f
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=368559
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@ -36,6 +36,9 @@
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# xargs -n1 | sort | uniq -d;
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# done
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# 20201211: hme(4) removed
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OLD_FILES+=usr/share/man/man4/hme.4.gz
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OLD_FILES+=usr/share/man/man4/if_hme.4.gz
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# 20201124: ping6(8) was merged into ping(8)
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OLD_FILES+=usr/lib/debug/sbin/ping6.debug
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OLD_FILES+=usr/share/man/man8/ping6.8.gz
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@ -180,7 +180,6 @@ MAN= aac.4 \
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gre.4 \
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h_ertt.4 \
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hifn.4 \
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hme.4 \
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hpet.4 \
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${_hpt27xx.4} \
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${_hptiop.4} \
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@ -665,7 +664,6 @@ MLINKS+=gpio.4 gpiobus.4
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MLINKS+=gpioths.4 dht11.4
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MLINKS+=gpioths.4 dht22.4
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MLINKS+=gre.4 if_gre.4
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MLINKS+=hme.4 if_hme.4
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MLINKS+=hpet.4 acpi_hpet.4
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MLINKS+=${_hptrr.4} ${_rr232x.4}
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MLINKS+=${_attimer.4} ${_i8254.4}
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@ -148,7 +148,6 @@ They have been applied to the following hardware drivers:
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.Xr et 4 ,
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.Xr fxp 4 ,
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.Xr gem 4 ,
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.Xr hme 4 ,
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.Xr igb 4 ,
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.Xr ixgbe 4 ,
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.Xr jme 4 ,
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@ -1,135 +0,0 @@
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.\" $NetBSD: hme.4,v 1.4 2003/02/14 15:20:18 grant Exp $
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.\"
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.\" Copyright (c) 2001 The NetBSD Foundation, Inc.
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.\" All rights reserved.
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.\"
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.\" This code is derived from software contributed to The NetBSD Foundation
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.\" by Klaus Klein.
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.\"
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.\" Redistribution and use in source and binary forms, with or without
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.\" modification, are permitted provided that the following conditions
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.\" are met:
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.\" 1. Redistributions of source code must retain the above copyright
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.\" notice, this list of conditions and the following disclaimer.
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.\" 2. Redistributions in binary form must reproduce the above copyright
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.\" notice, this list of conditions and the following disclaimer in the
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.\" documentation and/or other materials provided with the distribution.
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.\"
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.\" THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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.\" ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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.\" TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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.\" PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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.\" BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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.\" CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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.\" SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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.\" INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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.\" CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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.\" ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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.\" POSSIBILITY OF SUCH DAMAGE.
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.\"
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.\" $FreeBSD$
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.\"
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.Dd February 12, 2020
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.Dt HME 4
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.Os
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.Sh NAME
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.Nm hme
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.Nd "Sun Microelectronics STP2002-STQ Ethernet interfaces device driver"
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.Sh SYNOPSIS
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To compile this driver into the kernel,
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place the following lines in your
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kernel configuration file:
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.Bd -ragged -offset indent
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.Cd "device miibus"
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.Cd "device hme"
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.Ed
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.Pp
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Alternatively, to load the driver as a
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module at boot time, place the following line in
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.Xr loader.conf 5 :
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.Bd -literal -offset indent
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if_hme_load="YES"
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.Ed
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.Sh DEPRECATION NOTICE
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The
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.Nm
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driver is not present in
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.Fx 13.0
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and later.
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See https://github.com/freebsd/fcp/blob/master/fcp-0101.md for more
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information.
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.Sh DESCRIPTION
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The
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.Nm
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driver supports Sun Microelectronics STP2002-STQ
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.Dq Happy Meal Ethernet
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Fast Ethernet interfaces.
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.Pp
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All controllers supported by the
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.Nm
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driver have TCP checksum offload capability for both receive and transmit,
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support for the reception and transmission of extended frames for
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.Xr vlan 4
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and a 128-bit multicast hash filter.
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.Sh HARDWARE
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The
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.Nm
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driver supports the on-board Ethernet interfaces of many
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Sun
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.Tn UltraSPARC
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workstation and server models.
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.Pp
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Cards supported by the
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.Nm
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driver include:
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.Pp
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.Bl -bullet -compact
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.It
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Sun PCI SunSwift Adapter
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.Pq Dq SUNW,hme
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.It
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Sun SBus SunSwift Adapter
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.Dq ( hme
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and
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.Dq SUNW,hme )
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.It
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Sun PCI Sun100BaseT Adapter 2.0
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.Pq Dq SUNW,hme
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.It
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Sun SBus Sun100BaseT 2.0
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.Pq Dq SUNW,hme
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.It
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Sun PCI Quad FastEthernet Controller
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.Pq Dq SUNW,qfe
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.It
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Sun SBus Quad FastEthernet Controller
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.Pq Dq SUNW,qfe
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.El
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.Sh SEE ALSO
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.Xr altq 4 ,
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.Xr intro 4 ,
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.Xr miibus 4 ,
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.Xr netintro 4 ,
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.Xr vlan 4 ,
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.Xr eeprom 8 ,
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.Xr ifconfig 8
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.Rs
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.%T "STP2002QFP Fast Ethernet, Parallel Port, SCSI (FEPS) User's Guide"
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.%D April 1996
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.%A Sun Microelectronics
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.%U http://mediacast.sun.com/users/Barton808/media/STP2002QFP-FEPs_UG.pdf
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.Re
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.Sh HISTORY
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The
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.Nm
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driver first appeared in
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.Nx 1.5 .
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The first
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.Fx
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version to include it was
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.Fx 5.0 .
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.Sh AUTHORS
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The
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.Nm
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driver was written by
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.An Paul Kranenburg Aq Mt pk@NetBSD.org .
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@ -77,8 +77,6 @@ Agere ET1310 Gigabit Ethernet
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Intel EtherExpress PRO/100B
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.It Xr gem 4
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Sun ERI, Sun GEM and Apple GMAC Ethernet
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.It Xr hme 4
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Sun HME Ethernet
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.It Xr jme 4
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JMicron JMC250 Gigabit/JMC260 Fast Ethernet
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.It Xr lge 4
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@ -157,7 +155,6 @@ but as a result are not well behaved newbus device drivers.
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.Xr et 4 ,
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.Xr fxp 4 ,
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.Xr gem 4 ,
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.Xr hme 4 ,
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.Xr jme 4 ,
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.Xr lge 4 ,
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.Xr msk 4 ,
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|
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@ -172,7 +172,6 @@ These interfaces natively support long frames for
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.Xr fwe 4 ,
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.Xr fxp 4 ,
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.Xr gem 4 ,
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.Xr hme 4 ,
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.Xr le 4 ,
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.Xr nfe 4 ,
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.Xr rl 4 ,
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|
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@ -271,7 +271,6 @@ device dc # DEC/Intel 21143 and various workalikes
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device et # Agere ET1310 10/100/Gigabit Ethernet
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device fxp # Intel EtherExpress PRO/100B (82557, 82558)
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device gem # Sun GEM/Sun ERI/Apple GMAC
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device hme # Sun HME (Happy Meal Ethernet)
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device jme # JMicron JMC250 Gigabit/JMC260 Fast Ethernet
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device lge # Level 1 LXT1001 gigabit Ethernet
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device msk # Marvell/SysKonnect Yukon II Gigabit Ethernet
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@ -1867,7 +1867,6 @@ device xmphy # XaQti XMAC II
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# fxp: Intel EtherExpress Pro/100B
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# (hint of prefer_iomap can be done to prefer I/O instead of Mem mapping)
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# gem: Apple GMAC/Sun ERI/Sun GEM
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# hme: Sun HME (Happy Meal Ethernet)
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# jme: JMicron JMC260 Fast Ethernet/JMC250 Gigabit Ethernet based adapters.
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# le: AMD Am7900 LANCE and Am79C9xx PCnet
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# lge: Support for PCI gigabit ethernet adapters based on the Level 1
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@ -1956,7 +1955,6 @@ device et # Agere ET1310 10/100/Gigabit Ethernet
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device fxp # Intel EtherExpress PRO/100B (82557, 82558)
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envvar hint.fxp.0.prefer_iomap="0"
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device gem # Apple GMAC/Sun ERI/Sun GEM
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device hme # Sun HME (Happy Meal Ethernet)
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device jme # JMicron JMC250 Gigabit/JMC260 Fast Ethernet
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device lge # Level 1 LXT1001 gigabit Ethernet
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device mlxfw # Mellanox firmware update module
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@ -1816,8 +1816,6 @@ dev/gpio/gpiobus_if.m optional gpio
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dev/gpio/gpiopps.c optional gpiopps fdt
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dev/gpio/ofw_gpiobus.c optional fdt gpio
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dev/hifn/hifn7751.c optional hifn
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dev/hme/if_hme.c optional hme
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dev/hme/if_hme_pci.c optional hme pci
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dev/hptiop/hptiop.c optional hptiop scbus
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dev/hwpmc/hwpmc_logging.c optional hwpmc
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dev/hwpmc/hwpmc_mod.c optional hwpmc
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1750
sys/dev/hme/if_hme.c
1750
sys/dev/hme/if_hme.c
File diff suppressed because it is too large
Load diff
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@ -1,415 +0,0 @@
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/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2000 Matthew R. Green
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* Copyright (c) 2007 Marius Strobl <marius@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
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* SUCH DAMAGE.
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*
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* from: NetBSD: if_hme_pci.c,v 1.14 2004/03/17 08:58:23 martin Exp
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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/*
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* PCI front-end device driver for the HME ethernet device.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <sys/resource.h>
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#include <sys/socket.h>
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|
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#include <machine/bus.h>
|
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#if defined(__powerpc__)
|
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#include <dev/ofw/openfirm.h>
|
||||
#include <machine/ofw_machdep.h>
|
||||
#endif
|
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#include <machine/resource.h>
|
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|
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#include <sys/rman.h>
|
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|
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#include <net/ethernet.h>
|
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#include <net/if.h>
|
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#include <net/if_arp.h>
|
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#include <net/if_dl.h>
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#include <net/if_media.h>
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|
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#include <dev/mii/mii.h>
|
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#include <dev/mii/miivar.h>
|
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|
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#include <dev/pci/pcivar.h>
|
||||
#include <dev/pci/pcireg.h>
|
||||
|
||||
#include <dev/hme/if_hmereg.h>
|
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#include <dev/hme/if_hmevar.h>
|
||||
|
||||
#include "miibus_if.h"
|
||||
|
||||
struct hme_pci_softc {
|
||||
struct hme_softc hsc_hme; /* HME device */
|
||||
struct resource *hsc_sres;
|
||||
struct resource *hsc_ires;
|
||||
void *hsc_ih;
|
||||
};
|
||||
|
||||
static int hme_pci_probe(device_t);
|
||||
static int hme_pci_attach(device_t);
|
||||
static int hme_pci_detach(device_t);
|
||||
static int hme_pci_suspend(device_t);
|
||||
static int hme_pci_resume(device_t);
|
||||
|
||||
static device_method_t hme_pci_methods[] = {
|
||||
/* Device interface */
|
||||
DEVMETHOD(device_probe, hme_pci_probe),
|
||||
DEVMETHOD(device_attach, hme_pci_attach),
|
||||
DEVMETHOD(device_detach, hme_pci_detach),
|
||||
DEVMETHOD(device_suspend, hme_pci_suspend),
|
||||
DEVMETHOD(device_resume, hme_pci_resume),
|
||||
/* Can just use the suspend method here. */
|
||||
DEVMETHOD(device_shutdown, hme_pci_suspend),
|
||||
|
||||
/* MII interface */
|
||||
DEVMETHOD(miibus_readreg, hme_mii_readreg),
|
||||
DEVMETHOD(miibus_writereg, hme_mii_writereg),
|
||||
DEVMETHOD(miibus_statchg, hme_mii_statchg),
|
||||
|
||||
DEVMETHOD_END
|
||||
};
|
||||
|
||||
static driver_t hme_pci_driver = {
|
||||
"hme",
|
||||
hme_pci_methods,
|
||||
sizeof(struct hme_pci_softc)
|
||||
};
|
||||
|
||||
DRIVER_MODULE(hme, pci, hme_pci_driver, hme_devclass, 0, 0);
|
||||
MODULE_DEPEND(hme, pci, 1, 1, 1);
|
||||
MODULE_DEPEND(hme, ether, 1, 1, 1);
|
||||
|
||||
#define PCI_VENDOR_SUN 0x108e
|
||||
#define PCI_PRODUCT_SUN_EBUS 0x1000
|
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#define PCI_PRODUCT_SUN_HMENETWORK 0x1001
|
||||
|
||||
int
|
||||
hme_pci_probe(device_t dev)
|
||||
{
|
||||
|
||||
if (pci_get_vendor(dev) == PCI_VENDOR_SUN &&
|
||||
pci_get_device(dev) == PCI_PRODUCT_SUN_HMENETWORK) {
|
||||
device_set_desc(dev, "Sun HME 10/100 Ethernet");
|
||||
return (BUS_PROBE_DEFAULT);
|
||||
}
|
||||
return (ENXIO);
|
||||
}
|
||||
|
||||
int
|
||||
hme_pci_attach(device_t dev)
|
||||
{
|
||||
struct hme_pci_softc *hsc;
|
||||
struct hme_softc *sc;
|
||||
bus_space_tag_t memt;
|
||||
bus_space_handle_t memh;
|
||||
int i, error = 0;
|
||||
#if !defined(__powerpc__)
|
||||
device_t *children, ebus_dev;
|
||||
struct resource *ebus_rres;
|
||||
int j, slot;
|
||||
#endif
|
||||
|
||||
pci_enable_busmaster(dev);
|
||||
/*
|
||||
* Some Sun HMEs do have their intpin register bogusly set to 0,
|
||||
* although it should be 1. Correct that.
|
||||
*/
|
||||
if (pci_get_intpin(dev) == 0)
|
||||
pci_set_intpin(dev, 1);
|
||||
|
||||
hsc = device_get_softc(dev);
|
||||
sc = &hsc->hsc_hme;
|
||||
sc->sc_dev = dev;
|
||||
sc->sc_flags |= HME_PCI;
|
||||
mtx_init(&sc->sc_lock, device_get_nameunit(dev), MTX_NETWORK_LOCK,
|
||||
MTX_DEF);
|
||||
|
||||
/*
|
||||
* Map five register banks:
|
||||
*
|
||||
* bank 0: HME SEB registers: +0x0000
|
||||
* bank 1: HME ETX registers: +0x2000
|
||||
* bank 2: HME ERX registers: +0x4000
|
||||
* bank 3: HME MAC registers: +0x6000
|
||||
* bank 4: HME MIF registers: +0x7000
|
||||
*
|
||||
*/
|
||||
i = PCIR_BAR(0);
|
||||
hsc->hsc_sres = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
|
||||
&i, RF_ACTIVE);
|
||||
if (hsc->hsc_sres == NULL) {
|
||||
device_printf(dev, "could not map device registers\n");
|
||||
error = ENXIO;
|
||||
goto fail_mtx;
|
||||
}
|
||||
i = 0;
|
||||
hsc->hsc_ires = bus_alloc_resource_any(dev, SYS_RES_IRQ,
|
||||
&i, RF_SHAREABLE | RF_ACTIVE);
|
||||
if (hsc->hsc_ires == NULL) {
|
||||
device_printf(dev, "could not allocate interrupt\n");
|
||||
error = ENXIO;
|
||||
goto fail_sres;
|
||||
}
|
||||
memt = rman_get_bustag(hsc->hsc_sres);
|
||||
memh = rman_get_bushandle(hsc->hsc_sres);
|
||||
sc->sc_sebt = sc->sc_etxt = sc->sc_erxt = sc->sc_mact = sc->sc_mift =
|
||||
memt;
|
||||
bus_space_subregion(memt, memh, 0x0000, 0x1000, &sc->sc_sebh);
|
||||
bus_space_subregion(memt, memh, 0x2000, 0x1000, &sc->sc_etxh);
|
||||
bus_space_subregion(memt, memh, 0x4000, 0x1000, &sc->sc_erxh);
|
||||
bus_space_subregion(memt, memh, 0x6000, 0x1000, &sc->sc_mach);
|
||||
bus_space_subregion(memt, memh, 0x7000, 0x1000, &sc->sc_mifh);
|
||||
|
||||
#if defined(__powerpc__)
|
||||
OF_getetheraddr(dev, sc->sc_enaddr);
|
||||
#else
|
||||
/*
|
||||
* Dig out VPD (vital product data) and read NA (network address).
|
||||
*
|
||||
* The PCI HME is a PCIO chip, which is composed of two functions:
|
||||
* function 0: PCI-EBus2 bridge, and
|
||||
* function 1: HappyMeal Ethernet controller.
|
||||
*
|
||||
* The VPD of HME resides in the Boot PROM (PCI FCode) attached
|
||||
* to the EBus bridge and can't be accessed via the PCI capability
|
||||
* pointer.
|
||||
* ``Writing FCode 3.x Programs'' (newer ones, dated 1997 and later)
|
||||
* chapter 2 describes the data structure.
|
||||
*
|
||||
* We don't have a MI EBus driver since no EBus device exists
|
||||
* (besides the FCode PROM) on add-on HME boards. The ``no driver
|
||||
* attached'' message for function 0 therefore is what is expected.
|
||||
*/
|
||||
|
||||
#define PCI_ROMHDR_SIZE 0x1c
|
||||
#define PCI_ROMHDR_SIG 0x00
|
||||
#define PCI_ROMHDR_SIG_MAGIC 0xaa55 /* little endian */
|
||||
#define PCI_ROMHDR_PTR_DATA 0x18
|
||||
#define PCI_ROM_SIZE 0x18
|
||||
#define PCI_ROM_SIG 0x00
|
||||
#define PCI_ROM_SIG_MAGIC 0x52494350 /* "PCIR", endian */
|
||||
/* reversed */
|
||||
#define PCI_ROM_VENDOR 0x04
|
||||
#define PCI_ROM_DEVICE 0x06
|
||||
#define PCI_ROM_PTR_VPD 0x08
|
||||
#define PCI_VPDRES_BYTE0 0x00
|
||||
#define PCI_VPDRES_ISLARGE(x) ((x) & 0x80)
|
||||
#define PCI_VPDRES_LARGE_NAME(x) ((x) & 0x7f)
|
||||
#define PCI_VPDRES_TYPE_VPD 0x10 /* large */
|
||||
#define PCI_VPDRES_LARGE_LEN_LSB 0x01
|
||||
#define PCI_VPDRES_LARGE_LEN_MSB 0x02
|
||||
#define PCI_VPDRES_LARGE_DATA 0x03
|
||||
#define PCI_VPD_SIZE 0x03
|
||||
#define PCI_VPD_KEY0 0x00
|
||||
#define PCI_VPD_KEY1 0x01
|
||||
#define PCI_VPD_LEN 0x02
|
||||
#define PCI_VPD_DATA 0x03
|
||||
|
||||
#define HME_ROM_READ_N(n, offs) bus_space_read_ ## n (memt, memh, (offs))
|
||||
#define HME_ROM_READ_1(offs) HME_ROM_READ_N(1, (offs))
|
||||
#define HME_ROM_READ_2(offs) HME_ROM_READ_N(2, (offs))
|
||||
#define HME_ROM_READ_4(offs) HME_ROM_READ_N(4, (offs))
|
||||
|
||||
/* Search accompanying EBus bridge. */
|
||||
slot = pci_get_slot(dev);
|
||||
if (device_get_children(device_get_parent(dev), &children, &i) != 0) {
|
||||
device_printf(dev, "could not get children\n");
|
||||
error = ENXIO;
|
||||
goto fail_sres;
|
||||
}
|
||||
ebus_dev = NULL;
|
||||
for (j = 0; j < i; j++) {
|
||||
if (pci_get_class(children[j]) == PCIC_BRIDGE &&
|
||||
pci_get_vendor(children[j]) == PCI_VENDOR_SUN &&
|
||||
pci_get_device(children[j]) == PCI_PRODUCT_SUN_EBUS &&
|
||||
pci_get_slot(children[j]) == slot) {
|
||||
ebus_dev = children[j];
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (ebus_dev == NULL) {
|
||||
device_printf(dev, "could not find EBus bridge\n");
|
||||
error = ENXIO;
|
||||
goto fail_children;
|
||||
}
|
||||
|
||||
/* Map EBus bridge PROM registers. */
|
||||
i = PCIR_BAR(0);
|
||||
if ((ebus_rres = bus_alloc_resource_any(ebus_dev, SYS_RES_MEMORY,
|
||||
&i, RF_ACTIVE)) == NULL) {
|
||||
device_printf(dev, "could not map PROM registers\n");
|
||||
error = ENXIO;
|
||||
goto fail_children;
|
||||
}
|
||||
memt = rman_get_bustag(ebus_rres);
|
||||
memh = rman_get_bushandle(ebus_rres);
|
||||
|
||||
/* Read PCI Expansion ROM header. */
|
||||
if (HME_ROM_READ_2(PCI_ROMHDR_SIG) != PCI_ROMHDR_SIG_MAGIC ||
|
||||
(i = HME_ROM_READ_2(PCI_ROMHDR_PTR_DATA)) < PCI_ROMHDR_SIZE) {
|
||||
device_printf(dev, "unexpected PCI Expansion ROM header\n");
|
||||
error = ENXIO;
|
||||
goto fail_rres;
|
||||
}
|
||||
|
||||
/* Read PCI Expansion ROM data. */
|
||||
if (HME_ROM_READ_4(i + PCI_ROM_SIG) != PCI_ROM_SIG_MAGIC ||
|
||||
HME_ROM_READ_2(i + PCI_ROM_VENDOR) != pci_get_vendor(dev) ||
|
||||
HME_ROM_READ_2(i + PCI_ROM_DEVICE) != pci_get_device(dev) ||
|
||||
(j = HME_ROM_READ_2(i + PCI_ROM_PTR_VPD)) < i + PCI_ROM_SIZE) {
|
||||
device_printf(dev, "unexpected PCI Expansion ROM data\n");
|
||||
error = ENXIO;
|
||||
goto fail_rres;
|
||||
}
|
||||
|
||||
/*
|
||||
* Read PCI VPD.
|
||||
* SUNW,hme cards have a single large resource VPD-R tag
|
||||
* containing one NA. SUNW,qfe cards have four large resource
|
||||
* VPD-R tags containing one NA each (all four HME chips share
|
||||
* the same PROM).
|
||||
* The VPD used on both cards is not in PCI 2.2 standard format
|
||||
* however. The length in the resource header is in big endian
|
||||
* and the end tag is non-standard (0x79) and followed by an
|
||||
* all-zero "checksum" byte. Sun calls this a "Fresh Choice
|
||||
* Ethernet" VPD...
|
||||
*/
|
||||
/* Look at the end tag to determine whether this is a VPD with 4 NAs. */
|
||||
if (HME_ROM_READ_1(j + PCI_VPDRES_LARGE_DATA + PCI_VPD_SIZE +
|
||||
ETHER_ADDR_LEN) != 0x79 &&
|
||||
HME_ROM_READ_1(j + 4 * (PCI_VPDRES_LARGE_DATA + PCI_VPD_SIZE +
|
||||
ETHER_ADDR_LEN)) == 0x79)
|
||||
/* Use the Nth NA for the Nth HME on this SUNW,qfe. */
|
||||
j += slot * (PCI_VPDRES_LARGE_DATA + PCI_VPD_SIZE +
|
||||
ETHER_ADDR_LEN);
|
||||
if (PCI_VPDRES_ISLARGE(HME_ROM_READ_1(j + PCI_VPDRES_BYTE0)) == 0 ||
|
||||
PCI_VPDRES_LARGE_NAME(HME_ROM_READ_1(j + PCI_VPDRES_BYTE0)) !=
|
||||
PCI_VPDRES_TYPE_VPD ||
|
||||
(HME_ROM_READ_1(j + PCI_VPDRES_LARGE_LEN_LSB) << 8 |
|
||||
HME_ROM_READ_1(j + PCI_VPDRES_LARGE_LEN_MSB)) !=
|
||||
PCI_VPD_SIZE + ETHER_ADDR_LEN ||
|
||||
HME_ROM_READ_1(j + PCI_VPDRES_LARGE_DATA + PCI_VPD_KEY0) !=
|
||||
0x4e /* N */ ||
|
||||
HME_ROM_READ_1(j + PCI_VPDRES_LARGE_DATA + PCI_VPD_KEY1) !=
|
||||
0x41 /* A */ ||
|
||||
HME_ROM_READ_1(j + PCI_VPDRES_LARGE_DATA + PCI_VPD_LEN) !=
|
||||
ETHER_ADDR_LEN) {
|
||||
device_printf(dev, "unexpected PCI VPD\n");
|
||||
error = ENXIO;
|
||||
goto fail_rres;
|
||||
}
|
||||
bus_space_read_region_1(memt, memh, j + PCI_VPDRES_LARGE_DATA +
|
||||
PCI_VPD_DATA, sc->sc_enaddr, ETHER_ADDR_LEN);
|
||||
|
||||
fail_rres:
|
||||
bus_release_resource(ebus_dev, SYS_RES_MEMORY,
|
||||
rman_get_rid(ebus_rres), ebus_rres);
|
||||
fail_children:
|
||||
free(children, M_TEMP);
|
||||
if (error != 0)
|
||||
goto fail_sres;
|
||||
#endif
|
||||
|
||||
sc->sc_burst = 64; /* XXX */
|
||||
|
||||
/*
|
||||
* call the main configure
|
||||
*/
|
||||
if ((error = hme_config(sc)) != 0) {
|
||||
device_printf(dev, "could not be configured\n");
|
||||
goto fail_ires;
|
||||
}
|
||||
|
||||
if ((error = bus_setup_intr(dev, hsc->hsc_ires, INTR_TYPE_NET |
|
||||
INTR_MPSAFE, NULL, hme_intr, sc, &hsc->hsc_ih)) != 0) {
|
||||
device_printf(dev, "couldn't establish interrupt\n");
|
||||
hme_detach(sc);
|
||||
goto fail_ires;
|
||||
}
|
||||
return (0);
|
||||
|
||||
fail_ires:
|
||||
bus_release_resource(dev, SYS_RES_IRQ,
|
||||
rman_get_rid(hsc->hsc_ires), hsc->hsc_ires);
|
||||
fail_sres:
|
||||
bus_release_resource(dev, SYS_RES_MEMORY,
|
||||
rman_get_rid(hsc->hsc_sres), hsc->hsc_sres);
|
||||
fail_mtx:
|
||||
mtx_destroy(&sc->sc_lock);
|
||||
return (error);
|
||||
}
|
||||
|
||||
static int
|
||||
hme_pci_detach(device_t dev)
|
||||
{
|
||||
struct hme_pci_softc *hsc;
|
||||
struct hme_softc *sc;
|
||||
|
||||
hsc = device_get_softc(dev);
|
||||
sc = &hsc->hsc_hme;
|
||||
bus_teardown_intr(dev, hsc->hsc_ires, hsc->hsc_ih);
|
||||
hme_detach(sc);
|
||||
bus_release_resource(dev, SYS_RES_IRQ,
|
||||
rman_get_rid(hsc->hsc_ires), hsc->hsc_ires);
|
||||
bus_release_resource(dev, SYS_RES_MEMORY,
|
||||
rman_get_rid(hsc->hsc_sres), hsc->hsc_sres);
|
||||
mtx_destroy(&sc->sc_lock);
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
hme_pci_suspend(device_t dev)
|
||||
{
|
||||
struct hme_pci_softc *hsc;
|
||||
|
||||
hsc = device_get_softc(dev);
|
||||
hme_suspend(&hsc->hsc_hme);
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
hme_pci_resume(device_t dev)
|
||||
{
|
||||
struct hme_pci_softc *hsc;
|
||||
|
||||
hsc = device_get_softc(dev);
|
||||
hme_resume(&hsc->hsc_hme);
|
||||
return (0);
|
||||
}
|
||||
|
|
@ -1,311 +0,0 @@
|
|||
/*-
|
||||
* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
|
||||
*
|
||||
* Copyright (c) 1999 The NetBSD Foundation, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This code is derived from software contributed to The NetBSD Foundation
|
||||
* by Paul Kranenburg.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
|
||||
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* from: NetBSD: hmereg.h,v 1.16 2003/11/02 11:07:45 wiz Exp
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
/*
|
||||
* HME Shared Ethernet Block register offsets
|
||||
*/
|
||||
#define HME_SEBI_RESET (0*4)
|
||||
#define HME_SEBI_CFG (1*4)
|
||||
#define HME_SEBI_STAT (64*4)
|
||||
#define HME_SEBI_IMASK (65*4)
|
||||
|
||||
/* HME SEB bits. */
|
||||
#define HME_SEB_RESET_ETX 0x00000001 /* reset external transmitter */
|
||||
#define HME_SEB_RESET_ERX 0x00000002 /* reset external receiver */
|
||||
|
||||
#define HME_SEB_CFG_BURSTMASK 0x00000003 /* covers all burst bits */
|
||||
#define HME_SEB_CFG_BURST16 0x00000000 /* 16 byte bursts */
|
||||
#define HME_SEB_CFG_BURST32 0x00000001 /* 32 byte bursts */
|
||||
#define HME_SEB_CFG_BURST64 0x00000002 /* 64 byte bursts */
|
||||
#define HME_SEB_CFG_64BIT 0x00000004 /* extended transfer mode */
|
||||
#define HME_SEB_CFG_PARITY 0x00000008 /* parity check for DVMA/PIO */
|
||||
|
||||
#define HME_SEB_STAT_GOTFRAME 0x00000001 /* frame received */
|
||||
#define HME_SEB_STAT_RCNTEXP 0x00000002 /* rx frame count expired */
|
||||
#define HME_SEB_STAT_ACNTEXP 0x00000004 /* align error count expired */
|
||||
#define HME_SEB_STAT_CCNTEXP 0x00000008 /* crc error count expired */
|
||||
#define HME_SEB_STAT_LCNTEXP 0x00000010 /* length error count expired */
|
||||
#define HME_SEB_STAT_RFIFOVF 0x00000020 /* rx fifo overflow */
|
||||
#define HME_SEB_STAT_CVCNTEXP 0x00000040 /* code violation counter exp */
|
||||
#define HME_SEB_STAT_STSTERR 0x00000080 /* xif sqe test failed */
|
||||
#define HME_SEB_STAT_SENTFRAME 0x00000100 /* frame sent */
|
||||
#define HME_SEB_STAT_TFIFO_UND 0x00000200 /* tx fifo underrun */
|
||||
#define HME_SEB_STAT_MAXPKTERR 0x00000400 /* max-packet size error */
|
||||
#define HME_SEB_STAT_NCNTEXP 0x00000800 /* normal collision count exp */
|
||||
#define HME_SEB_STAT_ECNTEXP 0x00001000 /* excess collision count exp */
|
||||
#define HME_SEB_STAT_LCCNTEXP 0x00002000 /* late collision count exp */
|
||||
#define HME_SEB_STAT_FCNTEXP 0x00004000 /* first collision count exp */
|
||||
#define HME_SEB_STAT_DTIMEXP 0x00008000 /* defer timer expired */
|
||||
#define HME_SEB_STAT_RXTOHOST 0x00010000 /* pkt moved from rx fifo->memory */
|
||||
#define HME_SEB_STAT_NORXD 0x00020000 /* out of receive descriptors */
|
||||
#define HME_SEB_STAT_RXERR 0x00040000 /* rx DMA error */
|
||||
#define HME_SEB_STAT_RXLATERR 0x00080000 /* late error during rx DMA */
|
||||
#define HME_SEB_STAT_RXPERR 0x00100000 /* parity error during rx DMA */
|
||||
#define HME_SEB_STAT_RXTERR 0x00200000 /* tag error during rx DMA */
|
||||
#define HME_SEB_STAT_EOPERR 0x00400000 /* tx descriptor did not set EOP */
|
||||
#define HME_SEB_STAT_MIFIRQ 0x00800000 /* mif needs attention */
|
||||
#define HME_SEB_STAT_HOSTTOTX 0x01000000 /* pkt moved from memory->tx fifo */
|
||||
#define HME_SEB_STAT_TXALL 0x02000000 /* all pkts in fifo transmitted */
|
||||
#define HME_SEB_STAT_TXEACK 0x04000000 /* error during tx DMA */
|
||||
#define HME_SEB_STAT_TXLERR 0x08000000 /* late error during tx DMA */
|
||||
#define HME_SEB_STAT_TXPERR 0x10000000 /* parity error during tx DMA */
|
||||
#define HME_SEB_STAT_TXTERR 0x20000000 /* tag error during tx DMA */
|
||||
#define HME_SEB_STAT_SLVERR 0x40000000 /* pio access error */
|
||||
#define HME_SEB_STAT_SLVPERR 0x80000000 /* pio access parity error */
|
||||
#define HME_SEB_STAT_BITS "\177\020" \
|
||||
"b\0GOTFRAME\0b\1RCNTEXP\0b\2ACNTEXP\0" \
|
||||
"b\3CCNTEXP\0b\4LCNTEXP\0b\5RFIFOVF\0" \
|
||||
"b\6CVCNTEXP\0b\7STSTERR\0b\10SENTFRAME\0" \
|
||||
"b\11TFIFO_UND\0b\12MAXPKTERR\0b\13NCNTEXP\0" \
|
||||
"b\14ECNTEXP\0b\15LCCNTEXP\0b\16FCNTEXP\0" \
|
||||
"b\17DTIMEXP\0b\20RXTOHOST\0b\21NORXD\0" \
|
||||
"b\22RXERR\0b\23RXLATERR\0b\24RXPERR\0" \
|
||||
"b\25RXTERR\0b\26EOPERR\0b\27MIFIRQ\0" \
|
||||
"b\30HOSTTOTX\0b\31TXALL\0b\32XTEACK\0" \
|
||||
"b\33TXLERR\0b\34TXPERR\0b\35TXTERR\0" \
|
||||
"b\36SLVERR\0b\37SLVPERR\0\0"
|
||||
|
||||
#define HME_SEB_STAT_ALL_ERRORS \
|
||||
(HME_SEB_STAT_SLVPERR | HME_SEB_STAT_SLVERR | HME_SEB_STAT_TXTERR |\
|
||||
HME_SEB_STAT_TXPERR | HME_SEB_STAT_TXLERR | HME_SEB_STAT_TXEACK |\
|
||||
HME_SEB_STAT_EOPERR | HME_SEB_STAT_RXTERR | HME_SEB_STAT_RXPERR |\
|
||||
HME_SEB_STAT_RXLATERR | HME_SEB_STAT_RXERR | HME_SEB_STAT_NORXD |\
|
||||
HME_SEB_STAT_MAXPKTERR| HME_SEB_STAT_TFIFO_UND| HME_SEB_STAT_STSTERR |\
|
||||
HME_SEB_STAT_RFIFOVF)
|
||||
|
||||
#define HME_SEB_STAT_VLAN_ERRORS \
|
||||
(HME_SEB_STAT_SLVPERR | HME_SEB_STAT_SLVERR | HME_SEB_STAT_TXTERR |\
|
||||
HME_SEB_STAT_TXPERR | HME_SEB_STAT_TXLERR | HME_SEB_STAT_TXEACK |\
|
||||
HME_SEB_STAT_EOPERR | HME_SEB_STAT_RXTERR | HME_SEB_STAT_RXPERR |\
|
||||
HME_SEB_STAT_RXLATERR | HME_SEB_STAT_RXERR | HME_SEB_STAT_NORXD |\
|
||||
HME_SEB_STAT_TFIFO_UND| HME_SEB_STAT_STSTERR | HME_SEB_STAT_RFIFOVF)
|
||||
|
||||
#define HME_SEB_STAT_FATAL_ERRORS \
|
||||
(HME_SEB_STAT_SLVPERR | HME_SEB_STAT_SLVERR | HME_SEB_STAT_TXTERR |\
|
||||
HME_SEB_STAT_TXPERR | HME_SEB_STAT_TXLERR | HME_SEB_STAT_TXEACK |\
|
||||
HME_SEB_STAT_RXTERR | HME_SEB_STAT_RXPERR | HME_SEB_STAT_RXLATERR |\
|
||||
HME_SEB_STAT_RXERR)
|
||||
|
||||
/*
|
||||
* HME Transmitter register offsets
|
||||
*/
|
||||
#define HME_ETXI_PENDING (0*4) /* Pending/wakeup */
|
||||
#define HME_ETXI_CFG (1*4)
|
||||
#define HME_ETXI_RING (2*4) /* Descriptor Ring pointer */
|
||||
#define HME_ETXI_BBASE (3*4) /* Buffer base address (ro) */
|
||||
#define HME_ETXI_BDISP (4*4) /* Buffer displacement (ro) */
|
||||
#define HME_ETXI_FIFO_WPTR (5*4) /* FIFO write pointer */
|
||||
#define HME_ETXI_FIFO_SWPTR (6*4) /* FIFO shadow write pointer */
|
||||
#define HME_ETXI_FIFO_RPTR (7*4) /* FIFO read pointer */
|
||||
#define HME_ETXI_FIFO_SRPTR (8*4) /* FIFO shadow read pointer */
|
||||
#define HME_ETXI_FIFO_PKTCNT (9*4) /* FIFO packet counter */
|
||||
#define HME_ETXI_STATEMACHINE (10*4) /* State machine */
|
||||
#define HME_ETXI_RSIZE (11*4) /* Ring size */
|
||||
#define HME_ETXI_BPTR (12*4) /* Buffer pointer */
|
||||
|
||||
|
||||
/* TXI_PENDING bits */
|
||||
#define HME_ETX_TP_DMAWAKEUP 0x00000001 /* Start tx (rw, auto-clear) */
|
||||
|
||||
/* TXI_CFG bits */
|
||||
#define HME_ETX_CFG_DMAENABLE 0x00000001 /* Enable TX DMA */
|
||||
#define HME_ETX_CFG_FIFOTHRESH 0x000003fe /* TX fifo threshold */
|
||||
#define HME_ETX_CFG_IRQDAFTER 0x00000400 /* Intr after tx-fifo empty */
|
||||
#define HME_ETX_CFG_IRQDBEFORE 0x00000000 /* Intr before tx-fifo empty */
|
||||
|
||||
|
||||
/*
|
||||
* HME Receiver register offsets
|
||||
*/
|
||||
#define HME_ERXI_CFG (0*4)
|
||||
#define HME_ERXI_RING (1*4) /* Descriptor Ring pointer */
|
||||
#define HME_ERXI_BPTR (2*4) /* Data Buffer pointer (ro) */
|
||||
#define HME_ERXI_FIFO_WPTR (3*4) /* FIFO write pointer */
|
||||
#define HME_ERXI_FIFO_SWPTR (4*4) /* FIFO shadow write pointer */
|
||||
#define HME_ERXI_FIFO_RPTR (5*4) /* FIFO read pointer */
|
||||
#define HME_ERXI_FIFO_PKTCNT (6*4) /* FIFO packet counter */
|
||||
#define HME_ERXI_STATEMACHINE (7*4) /* State machine */
|
||||
|
||||
/* RXI_CFG bits */
|
||||
#define HME_ERX_CFG_DMAENABLE 0x00000001 /* Enable RX DMA */
|
||||
#define HME_ERX_CFG_FBO_MASK 0x00000038 /* RX first byte offset */
|
||||
#define HME_ERX_CFG_FBO_SHIFT 0x00000003
|
||||
#define HME_ERX_CFG_RINGSIZE32 0x00000000 /* Descriptor ring size: 32 */
|
||||
#define HME_ERX_CFG_RINGSIZE64 0x00000200 /* Descriptor ring size: 64 */
|
||||
#define HME_ERX_CFG_RINGSIZE128 0x00000400 /* Descriptor ring size: 128 */
|
||||
#define HME_ERX_CFG_RINGSIZE256 0x00000600 /* Descriptor ring size: 256 */
|
||||
#define HME_ERX_CFG_RINGSIZEMSK 0x00000600 /* Descriptor ring size: 256 */
|
||||
#define HME_ERX_CFG_CSUMSTART_MASK 0x007f0000 /* cksum offset mask */
|
||||
#define HME_ERX_CFG_CSUMSTART_SHIFT 16
|
||||
|
||||
/*
|
||||
* HME MAC-core register offsets
|
||||
*/
|
||||
#define HME_MACI_XIF (0*4)
|
||||
#define HME_MACI_TXSWRST (130*4) /* TX reset */
|
||||
#define HME_MACI_TXCFG (131*4) /* TX config */
|
||||
#define HME_MACI_JSIZE (139*4) /* TX jam size */
|
||||
#define HME_MACI_TXSIZE (140*4) /* TX max size */
|
||||
#define HME_MACI_NCCNT (144*4) /* TX normal collision cnt */
|
||||
#define HME_MACI_FCCNT (145*4) /* TX first collision cnt */
|
||||
#define HME_MACI_EXCNT (146*4) /* TX excess collision cnt */
|
||||
#define HME_MACI_LTCNT (147*4) /* TX late collision cnt */
|
||||
#define HME_MACI_RANDSEED (148*4) /* */
|
||||
#define HME_MACI_RXSWRST (194*4) /* RX reset */
|
||||
#define HME_MACI_RXCFG (195*4) /* RX config */
|
||||
#define HME_MACI_RXSIZE (196*4) /* RX max size */
|
||||
#define HME_MACI_MACADDR2 (198*4) /* MAC address */
|
||||
#define HME_MACI_MACADDR1 (199*4)
|
||||
#define HME_MACI_MACADDR0 (200*4)
|
||||
#define HME_MACI_HASHTAB3 (208*4) /* Address hash table */
|
||||
#define HME_MACI_HASHTAB2 (209*4)
|
||||
#define HME_MACI_HASHTAB1 (210*4)
|
||||
#define HME_MACI_HASHTAB0 (211*4)
|
||||
#define HME_MACI_AFILTER2 (212*4) /* Address filter */
|
||||
#define HME_MACI_AFILTER1 (213*4)
|
||||
#define HME_MACI_AFILTER0 (214*4)
|
||||
#define HME_MACI_AFILTER_MASK (215*4)
|
||||
|
||||
/* XIF config register. */
|
||||
#define HME_MAC_XIF_OE 0x00000001 /* Output driver enable */
|
||||
#define HME_MAC_XIF_XLBACK 0x00000002 /* Loopback-mode XIF enable */
|
||||
#define HME_MAC_XIF_MLBACK 0x00000004 /* Loopback-mode MII enable */
|
||||
#define HME_MAC_XIF_MIIENABLE 0x00000008 /* MII receive buffer enable */
|
||||
#define HME_MAC_XIF_SQENABLE 0x00000010 /* SQE test enable */
|
||||
#define HME_MAC_XIF_SQETWIN 0x000003e0 /* SQE time window */
|
||||
#define HME_MAC_XIF_LANCE 0x00000010 /* Lance mode enable */
|
||||
#define HME_MAC_XIF_LIPG0 0x000003e0 /* Lance mode IPG0 */
|
||||
|
||||
/* Transmit config register. */
|
||||
#define HME_MAC_TXCFG_ENABLE 0x00000001 /* Enable the transmitter */
|
||||
#define HME_MAC_TXCFG_SMODE 0x00000020 /* Enable slow transmit mode */
|
||||
#define HME_MAC_TXCFG_CIGN 0x00000040 /* Ignore transmit collisions */
|
||||
#define HME_MAC_TXCFG_FCSOFF 0x00000080 /* Do not emit FCS */
|
||||
#define HME_MAC_TXCFG_DBACKOFF 0x00000100 /* Disable backoff */
|
||||
#define HME_MAC_TXCFG_FULLDPLX 0x00000200 /* Enable full-duplex */
|
||||
#define HME_MAC_TXCFG_DGIVEUP 0x00000400 /* Don't give up on transmits */
|
||||
|
||||
/* Receive config register. */
|
||||
#define HME_MAC_RXCFG_ENABLE 0x00000001 /* Enable the receiver */
|
||||
#define HME_MAC_RXCFG_PSTRIP 0x00000020 /* Pad byte strip enable */
|
||||
#define HME_MAC_RXCFG_PMISC 0x00000040 /* Enable promiscuous mode */
|
||||
#define HME_MAC_RXCFG_DERR 0x00000080 /* Disable error checking */
|
||||
#define HME_MAC_RXCFG_DCRCS 0x00000100 /* Disable CRC stripping */
|
||||
#define HME_MAC_RXCFG_ME 0x00000200 /* Receive packets addressed to me */
|
||||
#define HME_MAC_RXCFG_PGRP 0x00000400 /* Enable promisc group mode */
|
||||
#define HME_MAC_RXCFG_HENABLE 0x00000800 /* Enable the hash filter */
|
||||
#define HME_MAC_RXCFG_AENABLE 0x00001000 /* Enable the address filter */
|
||||
|
||||
/*
|
||||
* HME MIF register offsets
|
||||
*/
|
||||
#define HME_MIFI_BB_CLK (0*4) /* bit-bang clock */
|
||||
#define HME_MIFI_BB_DATA (1*4) /* bit-bang data */
|
||||
#define HME_MIFI_BB_OE (2*4) /* bit-bang output enable */
|
||||
#define HME_MIFI_FO (3*4) /* frame output */
|
||||
#define HME_MIFI_CFG (4*4) /* */
|
||||
#define HME_MIFI_IMASK (5*4) /* Interrupt mask for status change */
|
||||
#define HME_MIFI_STAT (6*4) /* Status (ro, auto-clear) */
|
||||
#define HME_MIFI_SM (7*4) /* State machine (ro) */
|
||||
|
||||
/* MIF Configuration register */
|
||||
#define HME_MIF_CFG_PHY 0x00000001 /* PHY select */
|
||||
#define HME_MIF_CFG_PE 0x00000002 /* Poll enable */
|
||||
#define HME_MIF_CFG_BBMODE 0x00000004 /* Bit-bang mode */
|
||||
#define HME_MIF_CFG_PRADDR 0x000000f8 /* Poll register address */
|
||||
#define HME_MIF_CFG_MDI0 0x00000100 /* MDI_0 (ro) */
|
||||
#define HME_MIF_CFG_MDI1 0x00000200 /* MDI_1 (ro) */
|
||||
#define HME_MIF_CFG_PPADDR 0x00007c00 /* Poll phy address */
|
||||
|
||||
/* MIF Frame/Output register */
|
||||
#define HME_MIF_FO_ST 0xc0000000 /* Start of frame */
|
||||
#define HME_MIF_FO_ST_SHIFT 30 /* */
|
||||
#define HME_MIF_FO_OPC 0x30000000 /* Opcode */
|
||||
#define HME_MIF_FO_OPC_SHIFT 28 /* */
|
||||
#define HME_MIF_FO_PHYAD 0x0f800000 /* PHY Address */
|
||||
#define HME_MIF_FO_PHYAD_SHIFT 23 /* */
|
||||
#define HME_MIF_FO_REGAD 0x007c0000 /* Register Address */
|
||||
#define HME_MIF_FO_REGAD_SHIFT 18 /* */
|
||||
#define HME_MIF_FO_TAMSB 0x00020000 /* Turn-around MSB */
|
||||
#define HME_MIF_FO_TALSB 0x00010000 /* Turn-around LSB */
|
||||
#define HME_MIF_FO_DATA 0x0000ffff /* data to read or write */
|
||||
|
||||
/* Wired HME PHY addresses */
|
||||
#define HME_PHYAD_INTERNAL 1
|
||||
#define HME_PHYAD_EXTERNAL 0
|
||||
|
||||
/*
|
||||
* Buffer Descriptors.
|
||||
*/
|
||||
#define HME_XD_SIZE 8
|
||||
#define HME_XD_FLAGS(base, index) ((base) + ((index) * HME_XD_SIZE) + 0)
|
||||
#define HME_XD_ADDR(base, index) ((base) + ((index) * HME_XD_SIZE) + 4)
|
||||
#define HME_XD_GETFLAGS(p, b, i) \
|
||||
((p) ? le32toh(*((u_int32_t *)HME_XD_FLAGS(b,i))) : \
|
||||
(*((u_int32_t *)HME_XD_FLAGS(b,i))))
|
||||
#define HME_XD_SETFLAGS(p, b, i, f) do { \
|
||||
*((u_int32_t *)HME_XD_FLAGS(b,i)) = ((p) ? htole32((f)) : (f)); \
|
||||
} while(/* CONSTCOND */ 0)
|
||||
#define HME_XD_SETADDR(p, b, i, a) do { \
|
||||
*((u_int32_t *)HME_XD_ADDR(b,i)) = ((p) ? htole32((a)) : (a)); \
|
||||
} while(/* CONSTCOND */ 0)
|
||||
|
||||
/* Descriptor flag values */
|
||||
#define HME_XD_OWN 0x80000000 /* ownership: 1=hw, 0=sw */
|
||||
#define HME_XD_SOP 0x40000000 /* start of packet marker (tx) */
|
||||
#define HME_XD_OFL 0x40000000 /* buffer overflow (rx) */
|
||||
#define HME_XD_EOP 0x20000000 /* end of packet marker (tx) */
|
||||
#define HME_XD_TXCKSUM 0x10000000 /* checksum enable (tx) */
|
||||
#define HME_XD_RXLENMSK 0x3fff0000 /* packet length mask (rx) */
|
||||
#define HME_XD_RXLENSHIFT 16
|
||||
#define HME_XD_TXLENMSK 0x00003fff /* packet length mask (tx) */
|
||||
#define HME_XD_TXCKSUM_SSHIFT 14
|
||||
#define HME_XD_TXCKSUM_OSHIFT 20
|
||||
#define HME_XD_RXCKSUM 0x0000ffff /* packet checksum (rx) */
|
||||
|
||||
/* Macros to encode/decode the receive buffer size from the flags field */
|
||||
#define HME_XD_ENCODE_RSIZE(sz) \
|
||||
(((sz) << HME_XD_RXLENSHIFT) & HME_XD_RXLENMSK)
|
||||
#define HME_XD_DECODE_RSIZE(flags) \
|
||||
(((flags) & HME_XD_RXLENMSK) >> HME_XD_RXLENSHIFT)
|
||||
|
||||
/* Provide encode/decode macros for the transmit buffers for symmetry */
|
||||
#define HME_XD_ENCODE_TSIZE(sz) \
|
||||
(((sz) << 0) & HME_XD_TXLENMSK)
|
||||
#define HME_XD_DECODE_TSIZE(flags) \
|
||||
(((flags) & HME_XD_TXLENMSK) >> 0)
|
||||
|
||||
#define HME_MINRXALIGN 0x10
|
||||
#define HME_RXOFFS 2
|
||||
|
|
@ -1,160 +0,0 @@
|
|||
/*-
|
||||
* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
|
||||
*
|
||||
* Copyright (c) 1999 The NetBSD Foundation, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This code is derived from software contributed to The NetBSD Foundation
|
||||
* by Paul Kranenburg.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
|
||||
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* from: NetBSD: hmevar.h,v 1.5 2000/06/25 01:10:04 eeh Exp
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
#include <sys/callout.h>
|
||||
|
||||
/*
|
||||
* Number of receive and transmit descriptors. For each receive descriptor,
|
||||
* an mbuf cluster is allocated and set up to receive a packet, and a dma map
|
||||
* is created. Therefore, this number should not be too high to not waste
|
||||
* memory.
|
||||
* TX descriptors have no static cost, except for the memory directly allocated
|
||||
* for them. TX queue elements (the number of which is fixed by HME_NTXQ) hold
|
||||
* the software state for a transmit job; each has a dmamap allocated for it.
|
||||
* There may be multiple descriptors allocated to a single queue element.
|
||||
* HME_NTXQ and HME_NTXSEGS are completely arbitrary.
|
||||
*/
|
||||
#define HME_NRXDESC 128
|
||||
#define HME_NTXDESC 256
|
||||
#define HME_NTXQ 64
|
||||
#define HME_NTXSEGS 16
|
||||
|
||||
/* Maximum size of a mapped RX buffer. */
|
||||
#define HME_BUFSZ 1600
|
||||
|
||||
/*
|
||||
* RX DMA descriptor. The descriptors are preallocated; the dma map is
|
||||
* reused.
|
||||
*/
|
||||
struct hme_rxdesc {
|
||||
struct mbuf *hrx_m;
|
||||
bus_dmamap_t hrx_dmamap;
|
||||
};
|
||||
|
||||
/* Lazily leave at least one burst size grace space. */
|
||||
#define HME_DESC_RXLEN(sc, d) \
|
||||
ulmin(HME_BUFSZ, (d)->hrx_m->m_len - (sc)->sc_burst)
|
||||
|
||||
struct hme_txdesc {
|
||||
struct mbuf *htx_m;
|
||||
bus_dmamap_t htx_dmamap;
|
||||
int htx_lastdesc;
|
||||
STAILQ_ENTRY(hme_txdesc) htx_q;
|
||||
};
|
||||
|
||||
STAILQ_HEAD(hme_txdq, hme_txdesc);
|
||||
|
||||
struct hme_ring {
|
||||
/* Ring Descriptors */
|
||||
caddr_t rb_membase; /* Packet buffer: CPU address */
|
||||
bus_addr_t rb_dmabase; /* Packet buffer: DMA address */
|
||||
caddr_t rb_txd; /* Transmit descriptors */
|
||||
bus_addr_t rb_txddma; /* DMA address of same */
|
||||
caddr_t rb_rxd; /* Receive descriptors */
|
||||
bus_addr_t rb_rxddma; /* DMA address of same */
|
||||
|
||||
/* Ring Descriptor state */
|
||||
int rb_tdhead, rb_tdtail;
|
||||
int rb_rdtail;
|
||||
int rb_td_nbusy;
|
||||
|
||||
/* Descriptors */
|
||||
struct hme_rxdesc rb_rxdesc[HME_NRXDESC];
|
||||
struct hme_txdesc rb_txdesc[HME_NTXQ];
|
||||
|
||||
struct hme_txdq rb_txfreeq;
|
||||
struct hme_txdq rb_txbusyq;
|
||||
|
||||
bus_dmamap_t rb_spare_dmamap;
|
||||
};
|
||||
|
||||
struct hme_softc {
|
||||
struct ifnet *sc_ifp;
|
||||
struct ifmedia sc_ifmedia;
|
||||
device_t sc_dev;
|
||||
device_t sc_miibus;
|
||||
struct mii_data *sc_mii; /* MII media control */
|
||||
u_char sc_enaddr[ETHER_ADDR_LEN];
|
||||
struct callout sc_tick_ch; /* tick callout */
|
||||
int sc_wdog_timer; /* watchdog timer */
|
||||
|
||||
/* The following bus handles are to be provided by the bus front-end */
|
||||
bus_dma_tag_t sc_pdmatag; /* bus dma parent tag */
|
||||
bus_dma_tag_t sc_cdmatag; /* control bus dma tag */
|
||||
bus_dmamap_t sc_cdmamap; /* control bus dma handle */
|
||||
bus_dma_tag_t sc_rdmatag; /* RX bus dma tag */
|
||||
bus_dma_tag_t sc_tdmatag; /* RX bus dma tag */
|
||||
bus_space_handle_t sc_sebh; /* HME Global registers */
|
||||
bus_space_handle_t sc_erxh; /* HME ERX registers */
|
||||
bus_space_handle_t sc_etxh; /* HME ETX registers */
|
||||
bus_space_handle_t sc_mach; /* HME MAC registers */
|
||||
bus_space_handle_t sc_mifh; /* HME MIF registers */
|
||||
bus_space_tag_t sc_sebt; /* HME Global registers */
|
||||
bus_space_tag_t sc_erxt; /* HME ERX registers */
|
||||
bus_space_tag_t sc_etxt; /* HME ETX registers */
|
||||
bus_space_tag_t sc_mact; /* HME MAC registers */
|
||||
bus_space_tag_t sc_mift; /* HME MIF registers */
|
||||
int sc_burst; /* DVMA burst size in effect */
|
||||
int sc_phys[2]; /* MII instance -> PHY map */
|
||||
|
||||
u_int sc_flags;
|
||||
#define HME_LINK (1 << 0) /* link is up */
|
||||
#define HME_PCI (1 << 1) /* PCI busses are little-endian */
|
||||
|
||||
int sc_ifflags;
|
||||
int sc_csum_features;
|
||||
|
||||
/* Ring descriptor */
|
||||
struct hme_ring sc_rb;
|
||||
|
||||
struct mtx sc_lock;
|
||||
};
|
||||
|
||||
#define HME_LOCK(_sc) mtx_lock(&(_sc)->sc_lock)
|
||||
#define HME_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_lock)
|
||||
#define HME_LOCK_ASSERT(_sc, _what) mtx_assert(&(_sc)->sc_lock, (_what))
|
||||
|
||||
extern devclass_t hme_devclass;
|
||||
|
||||
int hme_config(struct hme_softc *);
|
||||
void hme_detach(struct hme_softc *);
|
||||
void hme_suspend(struct hme_softc *);
|
||||
void hme_resume(struct hme_softc *);
|
||||
void hme_intr(void *);
|
||||
|
||||
/* MII methods & callbacks */
|
||||
int hme_mii_readreg(device_t, int, int);
|
||||
int hme_mii_writereg(device_t, int, int, int);
|
||||
void hme_mii_statchg(device_t);
|
||||
|
|
@ -272,9 +272,7 @@ TUNABLE_INT("hw.skc.jumbo_disable", &jumbo_disable);
|
|||
* UDP packets in Tx as the hardware can't differenciate UDP packets from
|
||||
* TCP packets. 0 chcecksum value for UDP packet is an invalid one as it
|
||||
* means sender didn't perforam checksum computation. For the safety I
|
||||
* disabled UDP checksum offload capability at the moment. Alternatively
|
||||
* we can intrduce a LINK0/LINK1 flag as hme(4) did in its Tx checksum
|
||||
* offload routine.
|
||||
* disabled UDP checksum offload capability at the moment.
|
||||
*/
|
||||
#define SK_CSUM_FEATURES (CSUM_TCP)
|
||||
|
||||
|
|
|
|||
|
|
@ -241,7 +241,6 @@ device dc # DEC/Intel 21143 and various workalikes
|
|||
device et # Agere ET1310 10/100/Gigabit Ethernet
|
||||
device fxp # Intel EtherExpress PRO/100B (82557, 82558)
|
||||
device gem # Sun GEM/Sun ERI/Apple GMAC
|
||||
device hme # Sun HME (Happy Meal Ethernet)
|
||||
device jme # JMicron JMC250 Gigabit/JMC260 Fast Ethernet
|
||||
device lge # Level 1 LXT1001 gigabit Ethernet
|
||||
device msk # Marvell/SysKonnect Yukon II Gigabit Ethernet
|
||||
|
|
|
|||
|
|
@ -130,7 +130,6 @@ SUBDIR= \
|
|||
${_glxsb} \
|
||||
gpio \
|
||||
hifn \
|
||||
hme \
|
||||
${_hpt27xx} \
|
||||
${_hptiop} \
|
||||
${_hptmv} \
|
||||
|
|
|
|||
|
|
@ -1,9 +0,0 @@
|
|||
# $FreeBSD$
|
||||
|
||||
.PATH: ${SRCTOP}/sys/dev/hme
|
||||
|
||||
KMOD= if_hme
|
||||
SRCS= bus_if.h device_if.h if_hme.c if_hme_pci.c miibus_if.h
|
||||
SRCS+= pci_if.h
|
||||
|
||||
.include <bsd.kmod.mk>
|
||||
|
|
@ -5666,7 +5666,7 @@ pf_route6(struct mbuf **m, struct pf_rule *r, int dir, struct ifnet *oifp,
|
|||
* CSUM_DATA_VALID :
|
||||
* network driver performed cksum, needs to additional pseudo header
|
||||
* cksum computation with partial csum_data(i.e. lack of H/W support for
|
||||
* pseudo header, for instance hme(4), sk(4) and possibly gem(4))
|
||||
* pseudo header, for instance sk(4) and possibly gem(4))
|
||||
*
|
||||
* After validating the cksum of packet, set both flag CSUM_DATA_VALID and
|
||||
* CSUM_PSEUDO_HDR in order to avoid recomputation of the cksum in upper
|
||||
|
|
|
|||
Loading…
Reference in a new issue