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https://github.com/freebsd/freebsd-src
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Whitespace cleanup:
o Wrap sentences on to new lines o Cleanup trailing whitespace Found with: textproc/igor MFC after: 1 week X-MFC-With: r232157
This commit is contained in:
parent
3102cfe2e2
commit
9d496f5ab6
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=232158
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@ -176,7 +176,8 @@ option, since this matches the historic behavior of
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.Nm
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in
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.Fx . This option makes number parsing less strict and permits leading
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white space and an optional leading plus sign. In addition, empty operands
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white space and an optional leading plus sign.
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In addition, empty operands
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have an implied value of zero in numeric context.
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For historical reasons, defining the environment variable
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.Ev EXPR_COMPAT
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@ -300,7 +301,8 @@ standard, the use of string arguments
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.Va index ,
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or
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.Va match
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produces undefined results. In this version of
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produces undefined results.
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In this version of
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.Nm ,
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these arguments are treated just as their respective string values.
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.Pp
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@ -101,7 +101,8 @@ queries status of a process descriptor; currently only the
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.Fa st_ctime
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and
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.Fa st_mtime
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fields are defined. If the owner read, write, and execute bits are set then the
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fields are defined.
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If the owner read, write, and execute bits are set then the
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process represented by the process descriptor is still alive.
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.Pp
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.Xr poll 2
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@ -54,16 +54,16 @@ MIPS programmable PMCs support the following events:
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.Bl -tag -width indent
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.It Li CYCLE
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.Pq Event 0, Counter 0/1
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Total number of cycles.
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Total number of cycles.
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The performance counters are clocked by the
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top-level gated clock.
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top-level gated clock.
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If the core is built with that clock gater
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present, none of the counters will increment while the clock is
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stopped - due to a WAIT instruction.
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.It Li INSTR_EXECUTED
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.Pq Event 1, Counter 0/1
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Total number of instructions completed.
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.It Li BRANCH_COMPLETED
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.It Li BRANCH_COMPLETED
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.Pq Event 2, Counter 0
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Total number of branch instructions completed.
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.It Li BRANCH_MISPRED
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@ -85,9 +85,9 @@ If RPS use is disabled, JR $31 will not be predicted.
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.Pq Event 5, Counter 0
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Counts ITLB accesses that are due to fetches showing up in the
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instruction fetch stage of the pipeline and which do not use a fixed
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mapping or are not in unmapped space.
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mapping or are not in unmapped space.
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If an address is fetched twice from the pipe (as in the case of a
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cache miss), that instruction willcount as 2 ITLB accesses.
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cache miss), that instruction willcount as 2 ITLB accesses.
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Since each fetch gets us 2 instructions,there is one access marked per double
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word.
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.It Li ITLB_MISS
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@ -102,7 +102,8 @@ They are also ignored if there is some form of address error.
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Counts DTLB access including those in unmapped address spaces.
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.It Li DTLB_MISS
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.Pq Event 6, Counter 1
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Counts DTLB misses. Back to back misses that result in only one DTLB
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Counts DTLB misses.
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Back to back misses that result in only one DTLB
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entry getting refilled are counted as a single miss.
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.It Li JTLB_IACCESS
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.Pq Event 7, Counter 0
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@ -119,7 +120,8 @@ Data JTLB accesses.
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Counts data JTLB accesses that result in no match or a match on an invalid translation.
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.It Li IC_FETCH
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.Pq Event 9, Counter 0
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Counts every time the instruction cache is accessed. All replays,
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Counts every time the instruction cache is accessed.
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All replays,
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wasted fetches etc. are counted.
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For example, following a branch, even though the prediction is taken,
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the fall through access is counted.
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@ -179,7 +181,8 @@ when both stalls are active will only be counted once.
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replay traps (other than uTLB)
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.It Li STORE_COND_COMPLETED
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.Pq Event 19, Counter 0
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Conditional stores completed. Counts all events, including failed stores.
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Conditional stores completed.
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Counts all events, including failed stores.
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.It Li STORE_COND_FAILED
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.Pq Event 19, Counter 1
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Conditional store instruction that did not update memory.
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@ -189,7 +192,7 @@ different and the observed operating mode could change between them,
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causing some inaccuracy in the measured ratio.
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.It Li ICACHE_REQUESTS
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.Pq Event 20, Counter 0
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Note that this only counts PREFs that are actually attempted.
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Note that this only counts PREFs that are actually attempted.
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PREFs to uncached addresses or ones with translation errors are not counted
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.It Li ICACHE_HIT
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.Pq Event 20, Counter 1
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@ -214,7 +217,7 @@ Any type of exception taken.
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Counts cycles where the LSU is in fixup and cannot accept a new
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instruction from the ALU.
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Fixups are replays within the LSU that occur when an instruction needs
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to re-access the cache or the DTLB.
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to re-access the cache or the DTLB.
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.It Li IFU_CYCLES_STALLED
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.Pq Event 25, Counter 0
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Counts the number of cycles where the fetch unit is not providing a
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@ -256,7 +259,7 @@ Cycles where the main pipeline is stalled because of an index conflict
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in the Fill Store Buffer.
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.It Li DMISS_CYCLES
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.Pq Event 39, Counter 0
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Data miss is outstanding, but not necessarily stalling the pipeline.
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Data miss is outstanding, but not necessarily stalling the pipeline.
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The difference between this and D$ miss stall cycles can show the gain
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from non-blocking cache misses.
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.It Li L2_MISS_CYCLES
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@ -282,7 +285,8 @@ Counts all cycles where integer pipeline waits on CorExtend return data.
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Count all pipeline bubbles that are a result of multicycle ISPRAM
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access.
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Pipeline bubbles are defined as all cycles that IFU doesn't present an
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instruction to ALU. The four cycles after a redirect are not counted.
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instruction to ALU.
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The four cycles after a redirect are not counted.
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.It Li DSPRAM_STALL_CYCLES
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.Pq Event 43, Counter 1
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Counts stall cycles created by an instruction waiting for access to DSPRAM.
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@ -372,10 +376,10 @@ aliases supported by
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.Lb libpmc
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and the underlying hardware events used.
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.Bl -column "branch-mispredicts" "cpu_clk_unhalted.core_p"
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.It Em Alias Ta Em Event Ta
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.It Em Alias Ta Em Event Ta
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.It Li instructions Ta Li INSTR_EXECUTED Ta
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.It Li branches Ta Li BRANCH_COMPLETED Ta
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.It Li branch-mispredicts Ta Li BRANCH_MISPRED Ta
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.It Li branches Ta Li BRANCH_COMPLETED Ta
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.It Li branch-mispredicts Ta Li BRANCH_MISPRED Ta
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.El
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.Sh SEE ALSO
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.Xr pmc 3 ,
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@ -39,7 +39,7 @@ program.
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It contains declarations and parameter/key-options.
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The syntax is very simple,
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.D1 Li variable = value;
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and they can be grouped via a
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and they can be grouped via a
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.Em block
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declaration:
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.Bf Li
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@ -60,7 +60,7 @@ currently only supported authentication method is CHAP, with
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digest either MD5 or SHA.
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Default is none.
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.It Cm HeaderDigest
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a
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a
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.Em digest
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is calculated on the header of all iSCSI PDUs, and
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checked.
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@ -141,7 +141,7 @@ to the value specified.
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.It Cm maxluns
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overrides the compiled value of
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.Sy luns ,
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see
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see
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.Xr iscsi_initiator 4 .
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This value can only be reduced.
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.It Cm sockbufsize
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@ -185,7 +185,7 @@ myiscsi { # nickname
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targetaddress = iscsi1
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targetname = iqn.1900.com.com:sn.123456
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}
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chaptest {
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chaptest {
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targetaddress= 10.0.0.1;
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targetname = iqn.1900.com.com:sn.123456
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initiatorname= iqn.2005-01.il.ac.huji.cs:nobody
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@ -100,28 +100,36 @@ prompt before booting the kernel or stored in
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.Xr loader.conf 5 .
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.Bl -tag -width indent
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.It Va hw.cxgbe.ntxq10g
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The number of tx queues to use for a 10Gb port. The default is 16 or the number
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The number of tx queues to use for a 10Gb port.
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The default is 16 or the number
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of CPU cores in the system, whichever is less.
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.It Va hw.cxgbe.nrxq10g
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The number of rx queues to use for a 10Gb port. The default is 8 or the number
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The number of rx queues to use for a 10Gb port.
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The default is 8 or the number
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of CPU cores in the system, whichever is less.
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.It Va hw.cxgbe.ntxq1g
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The number of tx queues to use for a 1Gb port. The default is 4 or the number
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The number of tx queues to use for a 1Gb port.
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The default is 4 or the number
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of CPU cores in the system, whichever is less.
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.It Va hw.cxgbe.nrxq1g
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The number of rx queues to use for a 1Gb port. The default is 2 or the number
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The number of rx queues to use for a 1Gb port.
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The default is 2 or the number
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of CPU cores in the system, whichever is less.
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.It Va hw.cxgbe.nofldtxq10g
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The number of TOE tx queues to use for a 10Gb port. The default is 8 or the
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The number of TOE tx queues to use for a 10Gb port.
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The default is 8 or the
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number of CPU cores in the system, whichever is less.
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.It Va hw.cxgbe.nofldrxq10g
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The number of TOE rx queues to use for a 10Gb port. The default is 2 or the
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The number of TOE rx queues to use for a 10Gb port.
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The default is 2 or the
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number of CPU cores in the system, whichever is less.
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.It Va hw.cxgbe.nofldtxq1g
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The number of TOE tx queues to use for a 1Gb port. The default is 2 or the
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The number of TOE tx queues to use for a 1Gb port.
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The default is 2 or the
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number of CPU cores in the system, whichever is less.
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.It Va hw.cxgbe.nofldrxq1g
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The number of TOE rx queues to use for a 1Gb port. The default is 1.
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The number of TOE rx queues to use for a 1Gb port.
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The default is 1.
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.It Va hw.cxgbe.holdoff_timer_idx_10G
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.It Va hw.cxgbe.holdoff_timer_idx_1G
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The timer index value to use to delay interrupts.
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@ -149,7 +157,8 @@ ifconfig up).
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The size, in number of entries, of the descriptor ring used for a tx
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queue.
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A buf_ring of the same size is also allocated for additional
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software queuing. See
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software queuing.
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See
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.Xr ifnet 9 .
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The default value is 1024.
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Different cxgbe interfaces can be assigned different values via the
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@ -423,8 +423,8 @@ packets are received.
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As a result, it may throw out some good packets which
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have been received but not yet transferred from the card to main memory.
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.Pp
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The
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.Nm
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The
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.Nm
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driver is slow by today's standards.
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.Pp
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PC Card attachment supports the D-Link DMF650TX LAN/Modem card's Ethernet
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@ -54,8 +54,10 @@ umcs_load="YES"
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The
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.Nm
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driver provides support for various multiport serial adapters based on the MosCom
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MCS7820 and MCS7840 chips. They are 2- or 4-port adapters with full-featured
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16550-compatible UARTs and very flexible baud generators. Also, these chips
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MCS7820 and MCS7840 chips.
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They are 2- or 4-port adapters with full-featured
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16550-compatible UARTs and very flexible baud generators.
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Also, these chips
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support RS422/RS485 and IrDA operations.
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.Pp
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The device is accessed through the
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@ -200,7 +200,7 @@ to handle device added, removed or unknown events from the kernel.
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.Pq Vt bool
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Run
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.Xr ddb 8
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to install
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to install
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.Xr ddb 4
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scripts at boot time.
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.It Va ddb_config
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@ -1273,7 +1273,7 @@ options in this variable, in addition to the
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file.
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For instance, to configure an
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.Xr ath 4
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wireless device in station mode with an address obtained
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wireless device in station mode with an address obtained
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via DHCP, using WPA authentication and 802.11b mode, it is
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possible to use something like:
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.Bd -literal
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@ -1449,7 +1449,8 @@ Aliases should be set by
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.Va ifconfig_ Ns Ao Ar interface Ac Ns Va _alias Ns Aq Ar n
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with
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.Dq Li inet6
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keyword. For example:
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keyword.
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For example:
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.Bd -literal
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ifconfig_ed0_ipv6="inet6 2001:db8:1::1 prefixlen 64"
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ifconfig_ed0_alias0="inet6 2001:db8:2::1 prefixlen 64"
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|
@ -1552,14 +1553,17 @@ If
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.Dq Li AUTO
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is specified, it attempts to read a file
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.Pa /etc/ip6addrctl.conf
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first. If this file is found,
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first.
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If this file is found,
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.Xr ip6addrctl 8
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reads and installs it. If not found, a policy is automatically set
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reads and installs it.
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If not found, a policy is automatically set
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according to
|
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.Va ipv6_activate_all_interfaces
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variable; if the variable is set to
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.Dq Li YES
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the IPv6-preferred one is used. Otherwise IPv4-preferred.
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the IPv6-preferred one is used.
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Otherwise IPv4-preferred.
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.Pp
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The default value of
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.Va ip6addrctl_enable
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|
|
|
@ -86,7 +86,8 @@ If set to
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.Dq Li YES
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(case-insensitive) or
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.Dq Li 1 ,
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causes the menu to be displayed in color wherever possible. This includes the
|
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causes the menu to be displayed in color wherever possible.
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This includes the
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use of ANSI bold for numbers appearing to the left of menuitems and the use of
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special
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.Dq Li ansi
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|
@ -117,14 +118,18 @@ for additional information.
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|||
.It Va menu_timeout_command
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||||
The command to be executed after
|
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.Va autoboot_delay
|
||||
seconds if a key is not pressed. The default is
|
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seconds if a key is not pressed.
|
||||
The default is
|
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.Ic boot .
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.It Va loader_menu_timeout_x
|
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Sets the desired column position of the timeout countdown text. Default is 4.
|
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Sets the desired column position of the timeout countdown text.
|
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Default is 4.
|
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.It Va loader_menu_timeout_y
|
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Sets the desired row position of the timeout countdown text. Default is 23.
|
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Sets the desired row position of the timeout countdown text.
|
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Default is 23.
|
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.It Va loader_menu_title
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The text to display centered above the menu. Default is
|
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The text to display centered above the menu.
|
||||
Default is
|
||||
.Dq Li "Welcome to FreeBSD" .
|
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.It Va menu_caption[x]
|
||||
The text to be displayed for the numbered menuitem
|
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|
@ -132,7 +137,8 @@ The text to be displayed for the numbered menuitem
|
|||
.It Va menu_command[x]
|
||||
The command to be executed when the number associated with menuitem
|
||||
.Dq Li x
|
||||
is pressed. See the list of included FICL words below for some ideas.
|
||||
is pressed.
|
||||
See the list of included FICL words below for some ideas.
|
||||
.It Va menu_keycode[x]
|
||||
An optional decimal ASCII keycode to be associated with menuitem
|
||||
.Dq Li x .
|
||||
|
@ -201,7 +207,8 @@ menuitem (if configured).
|
|||
.It Va hint.acpi.0.disabled
|
||||
Effects the display of the
|
||||
.Va menu_acpi
|
||||
menuitem. If set, the menuitem will display
|
||||
menuitem.
|
||||
If set, the menuitem will display
|
||||
.Va toggled_text[x]
|
||||
.Va ( toggled_ansi[x]
|
||||
if
|
||||
|
@ -225,7 +232,8 @@ and
|
|||
.It Va menu_reboot
|
||||
If set, adds a built-in
|
||||
.Dq Li Reboot
|
||||
menuitem to the end of the last configured menuitem. If
|
||||
menuitem to the end of the last configured menuitem.
|
||||
If
|
||||
.Va menu_options
|
||||
is configured, the
|
||||
.Dq Li Reboot
|
||||
|
|
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