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armv8rng: Don't require toolchain to support FEAT_RNG

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We have the mechanism in place to support encoding system registers
explicitly, so use that rather than requiring LLVM 13+, which breaks our
current set of GitHub CI builds.

Fixes:	9eecef0521 ("Add an Armv8 rndr random number provider")
This commit is contained in:
Jessica Clarke 2023-12-01 23:59:07 +00:00
parent be7c095ac9
commit 9560ac4b63
2 changed files with 13 additions and 4 deletions
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9
sys/arm64/include/armreg.h
View file

@ -1981,6 +1981,15 @@
#define PMXEVTYPER_EL0_CRm 13
#define PMXEVTYPER_EL0_op2 1
/* RNDRRS */
#define RNDRRS MRS_REG(RNDRRS)
#define RNDRRS_REG MRS_REG_ALT_NAME(RNDRRS)
#define RNDRRS_op0 3
#define RNDRRS_op1 3
#define RNDRRS_CRn 2
#define RNDRRS_CRm 4
#define RNDRRS_op2 1
/* SCTLR_EL1 - System Control Register */
#define SCTLR_RES1 0x30d00800 /* Reserved ARMv8.0, write 1 */
#define SCTLR_M (UL(0x1) << 0)

8
sys/dev/random/armv8rng.c
View file

@ -59,10 +59,10 @@ random_rndr_read_one(u_long *buf)
loop = 10;
do {
__asm __volatile(
".arch_extension rng \n"
"mrs %0, rndrrs \n" /* Read the random number */
"cset %w1, ne \n" /* 1 on success, 0 on failure */
".arch_extension norng \n"
/* Read the random number */
"mrs %0, " __XSTRING(RNDRRS_REG) "\n"
/* 1 on success, 0 on failure */
"cset %w1, ne\n"
: "=&r" (val), "=&r"(ret) :: "cc");
} while (ret != 0 && --loop > 0);