mirror of
https://github.com/freebsd/freebsd-src
synced 2024-11-05 18:22:52 +00:00
- Make the NVRAM debug code compile and work.
- Get rid of a fiew uselessly `long' variables and casts to `long'. - Estimate the PCI clock for all chips, except C1010 for now (we should do that for each PCI BUS) - Refine a couple of C1010 errata work-arounds. - For now, make sure AIP generation is disabled for the C1010-66.
This commit is contained in:
Gerard Roudier
parent
5c0accbea6
commit
94d057fdf4
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=61051
3 changed files with 65 additions and 38 deletions
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@ -499,13 +499,16 @@ struct sym_reg {
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/*b4*/ u32 nc_dbms; /* Dynamic Block Move Selector */
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/*b8*/ u32 nc_dnad64; /* DMA Next Address 64 */
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/*bc*/ u16 nc_scntl4; /* C1010 only */
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#define U3EN 0x80 /* Enable Ultra 3 */
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#define AIPEN 0x40 /* Allow check upper byte lanes */
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#define U3EN 0x80 /* Enable Ultra 3 */
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#define AIPCKEN 0x40 /* AIP checking enable */
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/* Also enable AIP generation on C10-33*/
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#define XCLKH_DT 0x08 /* Extra clock of data hold on DT edge */
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#define XCLKH_ST 0x04 /* Extra clock of data hold on ST edge */
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#define XCLKS_DT 0x02 /* Extra clock of data set on DT edge */
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#define XCLKS_ST 0x01 /* Extra clock of data set on ST edge */
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/*be*/ u16 nc_aipcntl; /* Epat Control 1 C1010 only */
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/*be*/ u8 nc_aipcntl0; /* AIP Control 0 C1010 only */
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/*bf*/ u8 nc_aipcntl1; /* AIP Control 1 C1010 only */
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#define DISAIP 0x08 /* Disable AIP generation C10-66 only */
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/*c0*/ u32 nc_pmjad1; /* Phase Mismatch Jump Address 1 */
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/*c4*/ u32 nc_pmjad2; /* Phase Mismatch Jump Address 2 */
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/*c8*/ u8 nc_rbc; /* Remaining Byte Count */
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@ -551,12 +551,12 @@ static struct SYM_FWA_SCR SYM_FWA_SCR = {
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}/*-------------------------< DATAO_PHASE >----------------------*/,{
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/*
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* C1010-66 errata work-around.
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* SCNTL4 to be written prior to any DATA_OUT
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* phase if 33 MHz PCI BUS.
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* Extra clocks of data hold must be inserted
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* in DATA OUT phase on 33 MHz PCI BUS.
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* Patched with a NOOP for other chips.
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*/
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SCR_LOAD_REL (scntl4, 1),
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offsetof(struct sym_dsb, select.sel_scntl4),
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SCR_REG_REG (scntl4, SCR_OR, (XCLKH_DT|XCLKH_ST)),
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0,
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SCR_RETURN,
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0,
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}/*-------------------------< MSG_IN >---------------------------*/,{
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@ -57,7 +57,7 @@
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/* $FreeBSD$ */
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#define SYM_DRIVER_NAME "sym-1.5.3-20000506"
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#define SYM_DRIVER_NAME "sym-1.5.4-20000528"
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/* #define SYM_DEBUG_GENERIC_SUPPORT */
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@ -220,7 +220,7 @@ static __inline void sym_que_splice(struct sym_quehead *list,
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}
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#define sym_que_entry(ptr, type, member) \
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((type *)((char *)(ptr)-(unsigned long)(&((type *)0)->member)))
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((type *)((char *)(ptr)-(unsigned int)(&((type *)0)->member)))
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#define sym_insque(new, pos) __sym_que_add(new, pos, (pos)->flink)
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@ -388,8 +388,8 @@ static int sym_debug = 0;
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/*
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* Insert a delay in micro-seconds and milli-seconds.
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*/
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static void UDELAY(long us) { DELAY(us); }
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static void MDELAY(long ms) { while (ms--) UDELAY(1000); }
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static void UDELAY(int us) { DELAY(us); }
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static void MDELAY(int ms) { while (ms--) UDELAY(1000); }
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/*
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* Simple power of two buddy-like allocator.
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@ -1521,7 +1521,7 @@ struct sym_ccb {
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/*
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* Other fields.
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*/
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u_long ccb_ba; /* BUS address of this CCB */
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u32 ccb_ba; /* BUS address of this CCB */
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u_short tag; /* Tag for this transfer */
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/* NO_TAG means no tag */
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u_char target;
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@ -1718,8 +1718,8 @@ struct sym_hcb {
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u_char maxoffs_dt; /* Max scsi offset (DT) */
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u_char multiplier; /* Clock multiplier (1,2,4) */
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u_char clock_divn; /* Number of clock divisors */
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u_long clock_khz; /* SCSI clock frequency in KHz */
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u32 clock_khz; /* SCSI clock frequency in KHz */
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u32 pciclk_khz; /* Estimated PCI clock in KHz */
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/*
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* Start queue management.
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* It is filled up by the host processor and accessed by the
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@ -1967,11 +1967,14 @@ sym_fw2_patch(hcb_p np)
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* Remove a couple of work-arounds specific to C1010 if
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* they are not desirable. See `sym_fw2.h' for more details.
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*/
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if ((np->features & (FE_C10|FE_PCI66)) != (FE_C10|FE_PCI66)) {
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if (!(np->device_id == PCI_ID_LSI53C1010_2 &&
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/* np->revision_id < 0xff */ 1 &&
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np->pciclk_khz < 60000)) {
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scripta0->datao_phase[0] = cpu_to_scr(SCR_NO_OP);
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scripta0->datao_phase[1] = cpu_to_scr(0);
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}
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if ((np->features & (FE_C10|FE_PCI66)) != FE_C10) {
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if (!(np->device_id == PCI_ID_LSI53C1010 &&
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/* np->revision_id < 0xff */ 1)) {
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scripta0->sel_done[0] = cpu_to_scr(SCR_NO_OP);
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scripta0->sel_done[1] = cpu_to_scr(0);
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}
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@ -2337,7 +2340,7 @@ static void sym_int_sir (hcb_p np);
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static void sym_free_ccb (hcb_p np, ccb_p cp);
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static ccb_p sym_get_ccb (hcb_p np, u_char tn, u_char ln, u_char tag_order);
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static ccb_p sym_alloc_ccb (hcb_p np);
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static ccb_p sym_ccb_from_dsa (hcb_p np, u_long dsa);
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static ccb_p sym_ccb_from_dsa (hcb_p np, u32 dsa);
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static lcb_p sym_alloc_lcb (hcb_p np, u_char tn, u_char ln);
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static void sym_alloc_lcb_tags (hcb_p np, u_char tn, u_char ln);
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static int sym_snooptest (hcb_p np);
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@ -2489,8 +2492,7 @@ static void sym_xpt_done2(hcb_p np, union ccb *ccb, int cam_status)
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* calculations more simple.
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*/
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#define _5M 5000000
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static u_long div_10M[] =
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{2*_5M, 3*_5M, 4*_5M, 6*_5M, 8*_5M, 12*_5M, 16*_5M};
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static u32 div_10M[] = {2*_5M, 3*_5M, 4*_5M, 6*_5M, 8*_5M, 12*_5M, 16*_5M};
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/*
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* SYMBIOS chips allow burst lengths of 2, 4, 8, 16, 32, 64,
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@ -2597,7 +2599,7 @@ static void sym_save_initial_setting (hcb_p np)
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static int sym_prepare_setting(hcb_p np, struct sym_nvram *nvram)
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{
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u_char burst_max;
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u_long period;
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u32 period;
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int i;
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/*
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@ -2698,7 +2700,8 @@ static int sym_prepare_setting(hcb_p np, struct sym_nvram *nvram)
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* In dual channel mode, contention occurs if internal cycles
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* are used. Disable internal cycles.
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*/
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if (np->device_id == PCI_ID_LSI53C1010 && np->revision_id < 0x45)
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if (np->device_id == PCI_ID_LSI53C1010 &&
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/* np->revision_id < 0xff */ 1)
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np->rv_ccntl0 |= DILS;
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/*
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@ -3154,7 +3157,7 @@ static int sym_wakeup_done (hcb_p np)
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{
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ccb_p cp;
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int i, n;
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u_long dsa;
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u32 dsa;
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n = 0;
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i = np->dqueueget;
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@ -3172,8 +3175,8 @@ static int sym_wakeup_done (hcb_p np)
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++n;
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}
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else
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printf ("%s: bad DSA (%lx) in done queue.\n",
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sym_name(np), dsa);
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printf ("%s: bad DSA (%x) in done queue.\n",
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sym_name(np), (u_int) dsa);
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}
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np->dqueueget = i;
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@ -3206,7 +3209,7 @@ static void sym_flush_busy_queue (hcb_p np, int cam_status)
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static void sym_init (hcb_p np, int reason)
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{
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int i;
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u_long phys;
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u32 phys;
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/*
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* Reset chip if asked, otherwise just clear fifos.
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@ -3291,6 +3294,12 @@ static void sym_init (hcb_p np, int reason)
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OUTB (nc_stest3, TE); /* TolerANT enable */
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OUTB (nc_stime0, 0x0c); /* HTH disabled STO 0.25 sec */
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/*
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* For now, disable AIP generation on C1010-66.
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*/
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if (np->device_id == PCI_ID_LSI53C1010_2)
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OUTB (nc_aipcntl1, DISAIP);
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/*
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* C10101 Errata.
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* Errant SGE's when in narrow. Write bits 4 & 5 of
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@ -3298,7 +3307,8 @@ static void sym_init (hcb_p np, int reason)
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* that from SCRIPTS for each selection/reselection, but
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* I just don't want. :)
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*/
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if (np->device_id == PCI_ID_LSI53C1010 && np->revision_id < 0x45)
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if (np->device_id == PCI_ID_LSI53C1010 &&
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/* np->revision_id < 0xff */ 1)
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OUTB (nc_stest1, INB(nc_stest1) | 0x30);
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/*
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@ -3659,7 +3669,7 @@ static void sym_settrans(hcb_p np, ccb_p cp, u_char dt, u_char ofs,
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* Set misc. ultra enable bits.
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*/
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if (np->features & FE_C10) {
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uval = uval & ~U3EN;
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uval = uval & ~(U3EN|AIPCKEN);
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if (dt) {
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assert(np->features & FE_U3EN);
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uval |= U3EN;
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@ -5574,7 +5584,7 @@ static int sym_compute_residual(hcb_p np, ccb_p cp)
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dp_sgmin = SYM_CONF_MAX_SG - cp->segments;
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resid = -cp->ext_ofs;
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for (dp_sg = cp->ext_sg; dp_sg < SYM_CONF_MAX_SG; ++dp_sg) {
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u_long tmp = scr_to_cpu(cp->phys.data[dp_sg].size);
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u_int tmp = scr_to_cpu(cp->phys.data[dp_sg].size);
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resid += (tmp & 0xffffff);
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}
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@ -6028,7 +6038,7 @@ static void sym_nego_rejected(hcb_p np, tcb_p tp, ccb_p cp)
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void sym_int_sir (hcb_p np)
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{
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u_char num = INB (nc_dsps);
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u_long dsa = INL (nc_dsa);
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u32 dsa = INL (nc_dsa);
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ccb_p cp = sym_ccb_from_dsa(np, dsa);
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u_char target = INB (nc_sdid) & 0x0f;
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tcb_p tp = &np->target[target];
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@ -6582,7 +6592,7 @@ static ccb_p sym_alloc_ccb(hcb_p np)
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/*
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* Look up a CCB from a DSA value.
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*/
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static ccb_p sym_ccb_from_dsa(hcb_p np, u_long dsa)
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static ccb_p sym_ccb_from_dsa(hcb_p np, u32 dsa)
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{
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int hcode;
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ccb_p cp;
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@ -7046,14 +7056,20 @@ static void sym_getclock (hcb_p np, int mult)
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*/
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static int sym_getpciclock (hcb_p np)
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{
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static int f = 0;
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int f = 0;
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/* For the C10, this will not work */
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if (!f && !(np->features & FE_C10)) {
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/*
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* For the C1010-33, this doesn't work.
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* For the C1010-66, this will be tested when I'll have
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* such a beast to play with.
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*/
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if (!(np->features & FE_C10)) {
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OUTB (nc_stest1, SCLK); /* Use the PCI clock as SCSI clock */
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f = (int) sym_getfreq (np);
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OUTB (nc_stest1, 0);
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}
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np->pciclk_khz = f;
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return f;
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}
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@ -9456,7 +9472,7 @@ sym_Tekram_setup_target(hcb_p np, int target, Tekram_nvram *nvram)
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/*
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* Dump Symbios format NVRAM for debugging purpose.
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*/
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void sym_display_Symbios_nvram(hcb_p np, Symbios_nvram *nvram)
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static void sym_display_Symbios_nvram(hcb_p np, Symbios_nvram *nvram)
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{
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int i;
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@ -9488,8 +9504,8 @@ void sym_display_Symbios_nvram(hcb_p np, Symbios_nvram *nvram)
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/*
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* Dump TEKRAM format NVRAM for debugging purpose.
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*/
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static u_char Tekram_boot_delay[7] __initdata = {3, 5, 10, 20, 30, 60, 120};
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void sym_display_Tekram_nvram(hcb_p np, Tekram_nvram *nvram)
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static u_char Tekram_boot_delay[7] = {3, 5, 10, 20, 30, 60, 120};
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static void sym_display_Tekram_nvram(hcb_p np, Tekram_nvram *nvram)
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{
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int i, tags, boot_delay;
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char *rem;
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@ -9555,11 +9571,19 @@ int sym_read_nvram(hcb_p np, struct sym_nvram *nvp)
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* Try to read TEKRAM nvram if Symbios nvram not found.
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*/
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if (SYM_SETUP_SYMBIOS_NVRAM &&
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!sym_read_Symbios_nvram (np, &nvp->data.Symbios))
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!sym_read_Symbios_nvram (np, &nvp->data.Symbios)) {
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nvp->type = SYM_SYMBIOS_NVRAM;
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#ifdef SYM_CONF_DEBUG_NVRAM
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sym_display_Symbios_nvram(np, &nvp->data.Symbios);
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#endif
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}
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else if (SYM_SETUP_TEKRAM_NVRAM &&
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!sym_read_Tekram_nvram (np, &nvp->data.Tekram))
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!sym_read_Tekram_nvram (np, &nvp->data.Tekram)) {
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nvp->type = SYM_TEKRAM_NVRAM;
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#ifdef SYM_CONF_DEBUG_NVRAM
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sym_display_Tekram_nvram(np, &nvp->data.Tekram);
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#endif
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}
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else
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nvp->type = 0;
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#else
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