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Fix the ar724x shift calculation when writing to the PCI config space.

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This was preventing the ath driver from being loaded at runtime.
It worked fine when compiled statically into the kernel but not when
kldload'ed after the system booted.

The root cause was that PCIR_INTLINE (register 60) was being
overwritten by zeros when register 62 was being written to.
A subsequent read of this register would return 0, and thus
the rest of the PCI glue assumed an IRQ resource had already
been allocated.  This caused the device to fail to attach at
runtime as the device itself didn't contain any IRQ resources.

TODO: go back over the ar71xx and ar724x PCI config read/write
code and ensure it's correct.
This commit is contained in:
Adrian Chadd 2012-01-07 04:13:25 +00:00
parent 6d417c1c70
commit 93e26ff438
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=229765
1 changed files with 1 additions and 1 deletions
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2
sys/mips/atheros/ar724x_pci.c
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@ -93,7 +93,7 @@ ar724x_pci_write(uint32_t reg, uint32_t offset, uint32_t data, int bytes)
uint32_t val, mask, shift;
/* Register access is 32-bit aligned */
shift = 8 * (offset & (bytes % 4));
shift = (offset & 3) * 8;
if (bytes % 4)
mask = (1 << (bytes * 8)) - 1;
else