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https://github.com/freebsd/freebsd-src
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Retire broken snd_ds1 and snd_maestro drivers
In 2012 joel@ reported[1] that these were not functional, and they do not appear to have been fixed since. [1] https://lists.freebsd.org/pipermail/freebsd-multimedia/2012-January/012751.html Reported by: joel Relnotes: Yes Sponsored by: The FreeBSD Foundation
This commit is contained in:
Ed Maste
parent
1d7f6de5cf
commit
92e6b4712b
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@ -52,6 +52,10 @@
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# xargs -n1 | sort | uniq -d;
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# done
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# 20200318: snd_ds1 and snd_maestro drivers removed
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OLD_FILES+=usr/share/man/man4/snd_ds1.4.gz
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OLD_FILES+=usr/share/man/man4/snd_maestro.4.gz
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# 20220307: remove 330.news
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OLD_FILES+=etc/periodic/daily/330.news
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@ -505,7 +505,6 @@ MAN= aac.4 \
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snd_cmi.4 \
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snd_cs4281.4 \
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snd_csa.4 \
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snd_ds1.4 \
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snd_emu10k1.4 \
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snd_emu10kx.4 \
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snd_envy24.4 \
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@ -518,7 +517,6 @@ MAN= aac.4 \
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snd_hdspe.4 \
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snd_ich.4 \
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snd_maestro3.4 \
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snd_maestro.4 \
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snd_mss.4 \
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snd_neomagic.4 \
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snd_sbc.4 \
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@ -91,8 +91,6 @@ The following bridge device drivers are available:
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.It
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.Xr snd_davbus 4 (enabled by default on powerpc)
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.It
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.Xr snd_ds1 4
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.It
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.Xr snd_emu10k1 4
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.It
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.Xr snd_emu10kx 4 (enabled by default on amd64, i386)
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@ -115,8 +113,6 @@ The following bridge device drivers are available:
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.It
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.Xr snd_ich 4 (enabled by default on amd64, i386)
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.It
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.Xr snd_maestro 4
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.It
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.Xr snd_maestro3 4
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.It
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.Xr snd_mss 4
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@ -710,7 +706,6 @@ A device node is not created properly.
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.Xr snd_cs4281 4 ,
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.Xr snd_csa 4 ,
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.Xr snd_davbus 4 ,
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.Xr snd_ds1 4 ,
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.Xr snd_emu10k1 4 ,
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.Xr snd_emu10kx 4 ,
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.Xr snd_envy24 4 ,
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@ -722,7 +717,6 @@ A device node is not created properly.
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.Xr snd_hda 4 ,
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.Xr snd_hdspe 4 ,
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.Xr snd_ich 4 ,
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.Xr snd_maestro 4 ,
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.Xr snd_maestro3 4 ,
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.Xr snd_mss 4 ,
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.Xr snd_neomagic 4 ,
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@ -1,76 +0,0 @@
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.\" Copyright (c) 2004 Atte Peltomaki
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.\" All rights reserved.
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.\"
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.\" Redistribution and use in source and binary forms, with or without
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.\" modification, are permitted provided that the following conditions
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.\" are met:
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.\" 1. Redistributions of source code must retain the above copyright
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.\" notice, this list of conditions and the following disclaimer.
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.\" 2. Redistributions in binary form must reproduce the above copyright
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.\" notice, this list of conditions and the following disclaimer in the
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.\" documentation and/or other materials provided with the distribution.
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.\"
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.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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.\" SUCH DAMAGE.
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.\"
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.\" $FreeBSD$
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.\"
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.Dd March 18, 2022
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.Dt SND_DS1 4
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.Os
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.Sh NAME
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.Nm snd_ds1
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.Nd "Yamaha DS-1 PCI bridge device driver"
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.Sh SYNOPSIS
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To compile this driver into the kernel, place the following lines in your
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kernel configuration file:
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.Bd -ragged -offset indent
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.Cd "device sound"
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.Cd "device snd_ds1"
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.Ed
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.Pp
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Alternatively, to load the driver as a module at boot time, place the
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following line in
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.Xr loader.conf 5 :
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.Bd -literal -offset indent
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snd_ds1_load="YES"
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.Ed
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.Sh DESCRIPTION
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The
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.Nm
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bridge driver allows the generic audio driver
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.Xr sound 4
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to attach to the Yamaha DS-1 sound card.
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.Sh HARDWARE
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The
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.Nm
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driver supports the following sound cards:
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.Pp
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.Bl -bullet -compact
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.It
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Yamaha DS-1
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.It
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Yamaha DS-1E
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.El
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.Sh SEE ALSO
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.Xr sound 4
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.Sh HISTORY
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The
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.Nm
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device driver first appeared in
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.Fx 4.1 .
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.Pp
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This driver will be removed in
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.Fx 14 .
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Users who require it may have better luck with the audio/oss port or package.
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.Sh AUTHORS
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.An Cameron Grant Aq Mt cg@FreeBSD.org
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@ -1,81 +0,0 @@
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.\" Copyright (c) 2004 Jorge Mario G. Mazo
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.\" All rights reserved.
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.\"
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.\" Redistribution and use in source and binary forms, with or without
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.\" modification, are permitted provided that the following conditions
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.\" are met:
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.\" 1. Redistributions of source code must retain the above copyright
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.\" notice, this list of conditions and the following disclaimer.
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.\" 2. Redistributions in binary form must reproduce the above copyright
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.\" notice, this list of conditions and the following disclaimer in the
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.\" documentation and/or other materials provided with the distribution.
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.\"
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.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
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.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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.\" SUCH DAMAGE.
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.\"
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.\" $FreeBSD$
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.\"
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.Dd March 18, 2022
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.Dt SND_MAESTRO 4
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.Os
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.Sh NAME
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.Nm snd_maestro
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.Nd "ESS Maestro bridge device driver"
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.Sh SYNOPSIS
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To compile this driver into the kernel, place the following lines in your
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kernel configuration file:
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.Bd -ragged -offset indent
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.Cd "device sound"
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.Cd "device snd_maestro"
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.Ed
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.Pp
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Alternatively, to load the driver as a module at boot time, place the
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following line in
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.Xr loader.conf 5 :
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.Bd -literal -offset indent
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snd_maestro_load="YES"
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.Ed
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.Sh DESCRIPTION
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The
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.Nm
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bridge driver allows the generic audio driver
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.Xr sound 4
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to attach to ESS Maestro based sound chips.
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This chipset is very popular in notebook computers, but it is
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also very used in a wide selection of cheap OEM sound cards.
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.Sh HARDWARE
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The
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.Nm
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driver supports the following PCI sound cards:
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.Pp
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.Bl -bullet -compact
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.It
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ESS Technology Maestro-1
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.It
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ESS Technology Maestro-2
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.It
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ESS Technology Maestro-2E
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.El
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.Sh SEE ALSO
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.Xr snd_maestro3 4 ,
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.Xr sound 4
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.Sh HISTORY
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The
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.Nm
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device driver first appeared in
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.Fx 4.2 .
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.Pp
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This driver will be removed in
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.Fx 14 .
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.Sh AUTHORS
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This manual page was written by
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.An Jorge Mario G. Mazo Aq Mt jgutie11@eafit.edu.co .
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@ -2041,7 +2041,6 @@ device sound
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# snd_cs4281: Crystal Semiconductor CS4281 PCI.
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# snd_csa: Crystal Semiconductor CS461x/428x PCI. (except
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# 4281)
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# snd_ds1: Yamaha DS-1 PCI.
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# snd_emu10k1: Creative EMU10K1 PCI and EMU10K2 (Audigy) PCI.
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# snd_emu10kx: Creative SoundBlaster Live! and Audigy
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# snd_envy24: VIA Envy24 and compatible, needs snd_spicds.
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@ -2057,7 +2056,6 @@ device sound
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# snd_ich: Intel ICH AC'97 and some more audio controllers
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# embedded in a chipset, for example nVidia
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# nForce controllers.
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# snd_maestro: ESS Technology Maestro-1/2x PCI.
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# snd_maestro3: ESS Technology Maestro-3/Allegro PCI.
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# snd_mss: Microsoft Sound System ISA PnP/non-PnP.
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# snd_neomagic: Neomagic 256 AV/ZX PCI.
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@ -2082,7 +2080,6 @@ device snd_atiixp
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device snd_cmi
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device snd_cs4281
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device snd_csa
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device snd_ds1
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device snd_emu10k1
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device snd_emu10kx
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device snd_envy24
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@ -2094,7 +2091,6 @@ device snd_gusc
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device snd_hda
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device snd_hdspe
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device snd_ich
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device snd_maestro
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device snd_maestro3
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device snd_mss
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device snd_neomagic
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@ -3103,7 +3103,6 @@ dev/sound/pci/cmi.c optional snd_cmi pci
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dev/sound/pci/cs4281.c optional snd_cs4281 pci
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dev/sound/pci/csa.c optional snd_csa pci
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dev/sound/pci/csapcm.c optional snd_csa pci
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dev/sound/pci/ds1.c optional snd_ds1 pci
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dev/sound/pci/emu10k1.c optional snd_emu10k1 pci
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dev/sound/pci/emu10kx.c optional snd_emu10kx pci
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dev/sound/pci/emu10kx-pcm.c optional snd_emu10kx pci
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@ -3113,7 +3112,6 @@ dev/sound/pci/envy24ht.c optional snd_envy24ht pci
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dev/sound/pci/es137x.c optional snd_es137x pci
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dev/sound/pci/fm801.c optional snd_fm801 pci
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dev/sound/pci/ich.c optional snd_ich pci
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dev/sound/pci/maestro.c optional snd_maestro pci
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dev/sound/pci/maestro3.c optional snd_maestro3 pci
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dev/sound/pci/neomagic.c optional snd_neomagic pci
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dev/sound/pci/solo.c optional snd_solo pci
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@ -65,7 +65,6 @@ MODULE_DEPEND(snd_driver, snd_cmi, 1, 1, 1);
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MODULE_DEPEND(snd_driver, snd_cs4281, 1, 1, 1);
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MODULE_DEPEND(snd_driver, snd_csa, 1, 1, 1);
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MODULE_DEPEND(snd_driver, snd_csapcm, 1, 1, 1);
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MODULE_DEPEND(snd_driver, snd_ds1, 1, 1, 1);
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MODULE_DEPEND(snd_driver, snd_emu10kx, 1, 1, 1);
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MODULE_DEPEND(snd_driver, snd_envy24, 1, 1, 1);
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MODULE_DEPEND(snd_driver, snd_envy24ht, 1, 1, 1);
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@ -75,7 +74,6 @@ MODULE_DEPEND(snd_driver, snd_fm801, 1, 1, 1);
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MODULE_DEPEND(snd_driver, snd_gusc, 1, 1, 1);
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MODULE_DEPEND(snd_driver, snd_hda, 1, 1, 1);
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MODULE_DEPEND(snd_driver, snd_ich, 1, 1, 1);
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MODULE_DEPEND(snd_driver, snd_maestro, 1, 1, 1);
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MODULE_DEPEND(snd_driver, snd_maestro3, 1, 1, 1);
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MODULE_DEPEND(snd_driver, snd_mss, 1, 1, 1);
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MODULE_DEPEND(snd_driver, snd_neomagic, 1, 1, 1);
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File diff suppressed because it is too large
Load diff
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@ -1,147 +0,0 @@
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/*
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* =======================================================================
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* title : define
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* company : YAMAHA
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* author : Taichi Sugiyama
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* create Data : 28/Sep/99
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* =======================================================================
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* $FreeBSD$
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*/
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/* ----- YAMAHA DS-XG Devices -------------------------------------------- */
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#define YAMAHA 0x1073
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#define YMF724 0x0004
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#define YMF724F 0x000d
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#define YMF734 0x0005
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#define YMF737 0x0008
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#define YMF738 0x0020
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#define YMF740 0x000a
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#define YMF740C 0x000c
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#define YMF744 0x0010
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#define YMF754 0x0012
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#define YMF738_TEG 0x0006
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#define DEVICE4CH(x) ((x == YMF738) || (x == YMF744) || (x == YMF754))
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#define PCIR_DSXGCTRL 0x48
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/* ----- interrupt flag -------------------------------------------------- */
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#define YDSXG_DEFINT 0x01
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#define YDSXG_TIMERINT 0x02
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/* ----- AC97 ------------------------------------------------------------ */
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#define YDSXG_AC97TIMEOUT 1000
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#define YDSXG_AC97READCMD 0x8000
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#define YDSXG_AC97WRITECMD 0x0000
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#define YDSXG_AC97READFALSE 0xFFFF
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/* ----- AC97 register map _---------------------------------------------- */
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#define AC97R_GPIOSTATUS 0x54
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/* ----- work buffer ----------------------------------------------------- */
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#define DEF_WORKBUFFLENGTH 0x0400
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/* ----- register size --------------------------------------------------- */
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#define YDSXG_MAPLENGTH 0x8000
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#define YDSXG_DSPLENGTH 0x0080
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#define YDSXG_CTRLLENGTH 0x3000
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/* ----- register map ---------------------------------------------------- */
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#define YDSXGR_INTFLAG 0x0004
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#define YDSXGR_ACTIVITY 0x0006
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#define YDSXGR_GLOBALCTRL 0x0008
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#define YDSXGR_ZVCTRL 0x000A
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#define YDSXGR_TIMERCTRL 0x0010
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#define YDSXGR_TIMERCOUNT 0x0012
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#define YDSXGR_SPDIFOUTCTRL 0x0018
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#define YDSXGR_SPDIFOUTSTATUS 0x001C
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#define YDSXGR_EEPROMCTRL 0x0020
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#define YDSXGR_SPDIFINCTRL 0x0034
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#define YDSXGR_SPDIFINSTATUS 0x0038
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#define YDSXGR_DSPPROGRAMDL 0x0048
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#define YDSXGR_DLCNTRL 0x004C
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#define YDSXGR_GPIOININTFLAG 0x0050
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#define YDSXGR_GPIOININTENABLE 0x0052
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#define YDSXGR_GPIOINSTATUS 0x0054
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#define YDSXGR_GPIOOUTCTRL 0x0056
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#define YDSXGR_GPIOFUNCENABLE 0x0058
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#define YDSXGR_GPIOTYPECONFIG 0x005A
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#define YDSXGR_AC97CMDDATA 0x0060
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#define YDSXGR_AC97CMDADR 0x0062
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#define YDSXGR_PRISTATUSDATA 0x0064
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#define YDSXGR_PRISTATUSADR 0x0066
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#define YDSXGR_SECSTATUSDATA 0x0068
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#define YDSXGR_SECSTATUSADR 0x006A
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#define YDSXGR_SECCONFIG 0x0070
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#define YDSXGR_LEGACYOUTVOL 0x0080
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#define YDSXGR_LEGACYOUTVOLL 0x0080
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#define YDSXGR_LEGACYOUTVOLR 0x0082
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#define YDSXGR_NATIVEDACOUTVOL 0x0084
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#define YDSXGR_NATIVEDACOUTVOLL 0x0084
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#define YDSXGR_NATIVEDACOUTVOLR 0x0086
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#define YDSXGR_SPDIFOUTVOL 0x0088
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#define YDSXGR_SPDIFOUTVOLL 0x0088
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#define YDSXGR_SPDIFOUTVOLR 0x008A
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#define YDSXGR_AC3OUTVOL 0x008C
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#define YDSXGR_AC3OUTVOLL 0x008C
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#define YDSXGR_AC3OUTVOLR 0x008E
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#define YDSXGR_PRIADCOUTVOL 0x0090
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#define YDSXGR_PRIADCOUTVOLL 0x0090
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#define YDSXGR_PRIADCOUTVOLR 0x0092
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#define YDSXGR_LEGACYLOOPVOL 0x0094
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#define YDSXGR_LEGACYLOOPVOLL 0x0094
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#define YDSXGR_LEGACYLOOPVOLR 0x0096
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#define YDSXGR_NATIVEDACLOOPVOL 0x0098
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#define YDSXGR_NATIVEDACLOOPVOLL 0x0098
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#define YDSXGR_NATIVEDACLOOPVOLR 0x009A
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#define YDSXGR_SPDIFLOOPVOL 0x009C
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#define YDSXGR_SPDIFLOOPVOLL 0x009E
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#define YDSXGR_SPDIFLOOPVOLR 0x009E
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#define YDSXGR_AC3LOOPVOL 0x00A0
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#define YDSXGR_AC3LOOPVOLL 0x00A0
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#define YDSXGR_AC3LOOPVOLR 0x00A2
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#define YDSXGR_PRIADCLOOPVOL 0x00A4
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#define YDSXGR_PRIADCLOOPVOLL 0x00A4
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#define YDSXGR_PRIADCLOOPVOLR 0x00A6
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#define YDSXGR_NATIVEADCINVOL 0x00A8
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#define YDSXGR_NATIVEADCINVOLL 0x00A8
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#define YDSXGR_NATIVEADCINVOLR 0x00AA
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#define YDSXGR_NATIVEDACINVOL 0x00AC
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#define YDSXGR_NATIVEDACINVOLL 0x00AC
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#define YDSXGR_NATIVEDACINVOLR 0x00AE
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#define YDSXGR_BUF441OUTVOL 0x00B0
|
||||
#define YDSXGR_BUF441OUTVOLL 0x00B0
|
||||
#define YDSXGR_BUF441OUTVOLR 0x00B2
|
||||
#define YDSXGR_BUF441LOOPVOL 0x00B4
|
||||
#define YDSXGR_BUF441LOOPVOLL 0x00B4
|
||||
#define YDSXGR_BUF441LOOPVOLR 0x00B6
|
||||
#define YDSXGR_SPDIFOUTVOL2 0x00B8
|
||||
#define YDSXGR_SPDIFOUTVOL2L 0x00B8
|
||||
#define YDSXGR_SPDIFOUTVOL2R 0x00BA
|
||||
#define YDSXGR_SPDIFLOOPVOL2 0x00BC
|
||||
#define YDSXGR_SPDIFLOOPVOL2L 0x00BC
|
||||
#define YDSXGR_SPDIFLOOPVOL2R 0x00BE
|
||||
#define YDSXGR_ADCSLOTSR 0x00C0
|
||||
#define YDSXGR_RECSLOTSR 0x00C4
|
||||
#define YDSXGR_ADCFORMAT 0x00C8
|
||||
#define YDSXGR_RECFORMAT 0x00CC
|
||||
#define YDSXGR_P44SLOTSR 0x00D0
|
||||
#define YDSXGR_STATUS 0x0100
|
||||
#define YDSXGR_CTRLSELECT 0x0104
|
||||
#define YDSXGR_MODE 0x0108
|
||||
#define YDSXGR_SAMPLECOUNT 0x010C
|
||||
#define YDSXGR_NUMOFSAMPLES 0x0110
|
||||
#define YDSXGR_CONFIG 0x0114
|
||||
#define YDSXGR_PLAYCTRLSIZE 0x0140
|
||||
#define YDSXGR_RECCTRLSIZE 0x0144
|
||||
#define YDSXGR_EFFCTRLSIZE 0x0148
|
||||
#define YDSXGR_WORKSIZE 0x014C
|
||||
#define YDSXGR_MAPOFREC 0x0150
|
||||
#define YDSXGR_MAPOFEFFECT 0x0154
|
||||
#define YDSXGR_PLAYCTRLBASE 0x0158
|
||||
#define YDSXGR_RECCTRLBASE 0x015C
|
||||
#define YDSXGR_EFFCTRLBASE 0x0160
|
||||
#define YDSXGR_WORKBASE 0x0164
|
||||
#define YDSXGR_DSPINSTRAM 0x1000
|
||||
#define YDSXGR_CTRLINSTRAM 0x4000
|
||||
|
||||
/* ----- time out -------------------------------------------------------- */
|
||||
#define YDSXG_WORKBITTIMEOUT 250000
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -1,382 +0,0 @@
|
|||
/*-
|
||||
* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
|
||||
*
|
||||
* Copyright (c) 1999-2000 Taku YAMAMOTO <taku@cent.saitama-u.ac.jp>
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* maestro_reg.h,v 1.13 2001/11/11 18:29:46 taku Exp
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
#ifndef MAESTRO_REG_H_INCLUDED
|
||||
#define MAESTRO_REG_H_INCLUDED
|
||||
|
||||
/* -----------------------------
|
||||
* PCI config registers
|
||||
*/
|
||||
|
||||
/* Legacy emulation */
|
||||
#define CONF_LEGACY 0x40
|
||||
|
||||
#define LEGACY_DISABLED 0x8000
|
||||
|
||||
/* Chip configurations */
|
||||
#define CONF_MAESTRO 0x50
|
||||
#define MAESTRO_PMC 0x08000000
|
||||
#define MAESTRO_SPDIF 0x01000000
|
||||
#define MAESTRO_HWVOL 0x00800000
|
||||
#define MAESTRO_CHIBUS 0x00100000
|
||||
#define MAESTRO_POSTEDWRITE 0x00000080
|
||||
#define MAESTRO_DMA_PCITIMING 0x00000040
|
||||
#define MAESTRO_SWAP_LR 0x00000020
|
||||
|
||||
/* ACPI configurations */
|
||||
#define CONF_ACPI_STOPCLOCK 0x54
|
||||
#define ACPI_PART_2ndC_CLOCK 15
|
||||
#define ACPI_PART_CODEC_CLOCK 14
|
||||
#define ACPI_PART_978 13 /* Docking station or something */
|
||||
#define ACPI_PART_SPDIF 12
|
||||
#define ACPI_PART_GLUE 11 /* What? */
|
||||
#define ACPI_PART_DAA 10
|
||||
#define ACPI_PART_PCI_IF 9
|
||||
#define ACPI_PART_HW_VOL 8
|
||||
#define ACPI_PART_GPIO 7
|
||||
#define ACPI_PART_ASSP 6
|
||||
#define ACPI_PART_SB 5
|
||||
#define ACPI_PART_FM 4
|
||||
#define ACPI_PART_RINGBUS 3
|
||||
#define ACPI_PART_MIDI 2
|
||||
#define ACPI_PART_GAME_PORT 1
|
||||
#define ACPI_PART_WP 0
|
||||
|
||||
/* Power management */
|
||||
#define CONF_PM_PTR 0x34 /* BYTE R */
|
||||
#define PM_CID 0 /* BYTE R */
|
||||
#define PPMI_CID 1
|
||||
#define PM_CTRL 4 /* BYTE RW */
|
||||
#define PPMI_D0 0 /* Full power */
|
||||
#define PPMI_D1 1 /* Medium power */
|
||||
#define PPMI_D2 2 /* Low power */
|
||||
#define PPMI_D3 3 /* Turned off */
|
||||
|
||||
/* -----------------------------
|
||||
* I/O ports
|
||||
*/
|
||||
|
||||
/* Direct Sound Processor (aka WP) */
|
||||
#define PORT_DSP_DATA 0x00 /* WORD RW */
|
||||
#define PORT_DSP_INDEX 0x02 /* WORD RW */
|
||||
#define PORT_INT_STAT 0x04 /* WORD RW */
|
||||
#define PORT_SAMPLE_CNT 0x06 /* WORD RO */
|
||||
|
||||
/* WaveCache */
|
||||
#define PORT_WAVCACHE_INDEX 0x10 /* WORD RW */
|
||||
#define PORT_WAVCACHE_DATA 0x12 /* WORD RW */
|
||||
#define WAVCACHE_PCMBAR 0x1fc
|
||||
#define WAVCACHE_WTBAR 0x1f0
|
||||
#define WAVCACHE_BASEADDR_SHIFT 12
|
||||
|
||||
#define WAVCACHE_CHCTL_ADDRTAG_MASK 0xfff8
|
||||
#define WAVCACHE_CHCTL_U8 0x0004
|
||||
#define WAVCACHE_CHCTL_STEREO 0x0002
|
||||
#define WAVCACHE_CHCTL_DECREMENTAL 0x0001
|
||||
|
||||
#define PORT_WAVCACHE_CTRL 0x14 /* WORD RW */
|
||||
#define WAVCACHE_EXTRA_CH_ENABLED 0x0200
|
||||
#define WAVCACHE_ENABLED 0x0100
|
||||
#define WAVCACHE_CH_60_ENABLED 0x0080
|
||||
#define WAVCACHE_WTSIZE_MASK 0x0060
|
||||
#define WAVCACHE_WTSIZE_1MB 0x0000
|
||||
#define WAVCACHE_WTSIZE_2MB 0x0020
|
||||
#define WAVCACHE_WTSIZE_4MB 0x0040
|
||||
#define WAVCACHE_WTSIZE_8MB 0x0060
|
||||
#define WAVCACHE_SGC_MASK 0x000c
|
||||
#define WAVCACHE_SGC_DISABLED 0x0000
|
||||
#define WAVCACHE_SGC_40_47 0x0004
|
||||
#define WAVCACHE_SGC_32_47 0x0008
|
||||
#define WAVCACHE_TESTMODE 0x0001
|
||||
|
||||
/* Host Interruption */
|
||||
#define PORT_HOSTINT_CTRL 0x18 /* WORD RW */
|
||||
#define HOSTINT_CTRL_SOFT_RESET 0x8000
|
||||
#define HOSTINT_CTRL_DSOUND_RESET 0x4000
|
||||
#define HOSTINT_CTRL_HW_VOL_TO_PME 0x0400
|
||||
#define HOSTINT_CTRL_CLKRUN_ENABLED 0x0100
|
||||
#define HOSTINT_CTRL_HWVOL_ENABLED 0x0040
|
||||
#define HOSTINT_CTRL_ASSP_INT_ENABLED 0x0010
|
||||
#define HOSTINT_CTRL_ISDN_INT_ENABLED 0x0008
|
||||
#define HOSTINT_CTRL_DSOUND_INT_ENABLED 0x0004
|
||||
#define HOSTINT_CTRL_MPU401_INT_ENABLED 0x0002
|
||||
#define HOSTINT_CTRL_SB_INT_ENABLED 0x0001
|
||||
|
||||
#define PORT_HOSTINT_STAT 0x1a /* BYTE RW */
|
||||
#define HOSTINT_STAT_HWVOL 0x40
|
||||
#define HOSTINT_STAT_ASSP 0x10
|
||||
#define HOSTINT_STAT_ISDN 0x08
|
||||
#define HOSTINT_STAT_DSOUND 0x04
|
||||
#define HOSTINT_STAT_MPU401 0x02
|
||||
#define HOSTINT_STAT_SB 0x01
|
||||
|
||||
/* Hardware volume */
|
||||
#define PORT_HWVOL_CTRL 0x1b /* BYTE RW */
|
||||
#define HWVOL_CTRL_SPLIT_SHADOW 0x01
|
||||
|
||||
#define PORT_HWVOL_VOICE_SHADOW 0x1c /* BYTE RW */
|
||||
#define PORT_HWVOL_VOICE 0x1d /* BYTE RW */
|
||||
#define PORT_HWVOL_MASTER_SHADOW 0x1e /* BYTE RW */
|
||||
#define PORT_HWVOL_MASTER 0x1f /* BYTE RW */
|
||||
#define HWVOL_NOP 0x88
|
||||
#define HWVOL_MUTE 0x11
|
||||
#define HWVOL_UP 0xaa
|
||||
#define HWVOL_DOWN 0x66
|
||||
|
||||
/* CODEC */
|
||||
#define PORT_CODEC_CMD 0x30 /* BYTE W */
|
||||
#define CODEC_CMD_READ 0x80
|
||||
#define CODEC_CMD_WRITE 0x00
|
||||
#define CODEC_CMD_ADDR_MASK 0x7f
|
||||
|
||||
#define PORT_CODEC_STAT 0x30 /* BYTE R */
|
||||
#define CODEC_STAT_MASK 0x01
|
||||
#define CODEC_STAT_RW_DONE 0x00
|
||||
#define CODEC_STAT_PROGLESS 0x01
|
||||
|
||||
#define PORT_CODEC_REG 0x32 /* WORD RW */
|
||||
|
||||
/* Ring bus control */
|
||||
#define PORT_RINGBUS_CTRL 0x34 /* DWORD RW */
|
||||
#define RINGBUS_CTRL_I2S_ENABLED 0x80000000
|
||||
#define RINGBUS_CTRL_RINGBUS_ENABLED 0x20000000
|
||||
#define RINGBUS_CTRL_ACLINK_ENABLED 0x10000000
|
||||
#define RINGBUS_CTRL_AC97_SWRESET 0x08000000
|
||||
|
||||
#define RINGBUS_SRC_MIC 20
|
||||
#define RINGBUS_SRC_I2S 16
|
||||
#define RINGBUS_SRC_ADC 12
|
||||
#define RINGBUS_SRC_MODEM 8
|
||||
#define RINGBUS_SRC_DSOUND 4
|
||||
#define RINGBUS_SRC_ASSP 0
|
||||
|
||||
#define RINGBUS_DEST_MONORAL 000
|
||||
#define RINGBUS_DEST_STEREO 010
|
||||
#define RINGBUS_DEST_NONE 0
|
||||
#define RINGBUS_DEST_DAC 1
|
||||
#define RINGBUS_DEST_MODEM_IN 2
|
||||
#define RINGBUS_DEST_RESERVED3 3
|
||||
#define RINGBUS_DEST_DSOUND_IN 4
|
||||
#define RINGBUS_DEST_ASSP_IN 5
|
||||
|
||||
/* Ring bus control B */
|
||||
#define PORT_RINGBUS_CTRL_B 0x38 /* BYTE RW */
|
||||
#define RINGBUS_CTRL_SSPE 0x40
|
||||
#define RINGBUS_CTRL_2ndCODEC 0x20
|
||||
#define RINGBUS_CTRL_SPDIF 0x10
|
||||
#define RINGBUS_CTRL_ITB_DISABLE 0x08
|
||||
#define RINGBUS_CTRL_CODEC_ID_MASK 0x03
|
||||
#define RINGBUS_CTRL_CODEC_ID_AC98 2
|
||||
|
||||
/* General Purpose I/O */
|
||||
#define PORT_GPIO_DATA 0x60 /* WORD RW */
|
||||
#define PORT_GPIO_MASK 0x64 /* WORD RW */
|
||||
#define PORT_GPIO_DIR 0x68 /* WORD RW */
|
||||
|
||||
/* Application Specific Signal Processor */
|
||||
#define PORT_ASSP_MEM_INDEX 0x80 /* DWORD RW */
|
||||
#define PORT_ASSP_MEM_DATA 0x84 /* WORD RW */
|
||||
#define PORT_ASSP_CTRL_A 0xa2 /* BYTE RW */
|
||||
#define PORT_ASSP_CTRL_B 0xa4 /* BYTE RW */
|
||||
#define PORT_ASSP_CTRL_C 0xa6 /* BYTE RW */
|
||||
#define PORT_ASSP_HOST_WR_INDEX 0xa8 /* BYTE W */
|
||||
#define PORT_ASSP_HOST_WR_DATA 0xaa /* BYTE RW */
|
||||
#define PORT_ASSP_INT_STAT 0xac /* BYTE RW */
|
||||
|
||||
/* -----------------------------
|
||||
* Wave Processor Indexed Data Registers.
|
||||
*/
|
||||
|
||||
#define WPREG_DATA_PORT 0
|
||||
#define WPREG_CRAM_PTR 1
|
||||
#define WPREG_CRAM_DATA 2
|
||||
#define WPREG_WAVE_DATA 3
|
||||
#define WPREG_WAVE_PTR_LOW 4
|
||||
#define WPREG_WAVE_PTR_HIGH 5
|
||||
|
||||
#define WPREG_TIMER_FREQ 6
|
||||
#define WP_TIMER_FREQ_PRESCALE_MASK 0x00e0 /* actual - 9 */
|
||||
#define WP_TIMER_FREQ_PRESCALE_SHIFT 5
|
||||
#define WP_TIMER_FREQ_DIVIDE_MASK 0x001f
|
||||
#define WP_TIMER_FREQ_DIVIDE_SHIFT 0
|
||||
|
||||
#define WPREG_WAVE_ROMRAM 7
|
||||
#define WP_WAVE_VIRTUAL_ENABLED 0x0400
|
||||
#define WP_WAVE_8BITRAM_ENABLED 0x0200
|
||||
#define WP_WAVE_DRAM_ENABLED 0x0100
|
||||
#define WP_WAVE_RAMSPLIT_MASK 0x00ff
|
||||
#define WP_WAVE_RAMSPLIT_SHIFT 0
|
||||
|
||||
#define WPREG_BASE 12
|
||||
#define WP_PARAOUT_BASE_MASK 0xf000
|
||||
#define WP_PARAOUT_BASE_SHIFT 12
|
||||
#define WP_PARAIN_BASE_MASK 0x0f00
|
||||
#define WP_PARAIN_BASE_SHIFT 8
|
||||
#define WP_SERIAL0_BASE_MASK 0x00f0
|
||||
#define WP_SERIAL0_BASE_SHIFT 4
|
||||
#define WP_SERIAL1_BASE_MASK 0x000f
|
||||
#define WP_SERIAL1_BASE_SHIFT 0
|
||||
|
||||
#define WPREG_TIMER_ENABLE 17
|
||||
#define WPREG_TIMER_START 23
|
||||
|
||||
/* -----------------------------
|
||||
* Audio Processing Unit.
|
||||
*/
|
||||
#define APUREG_APUTYPE 0
|
||||
#define APU_DMA_ENABLED 0x4000
|
||||
#define APU_INT_ON_LOOP 0x2000
|
||||
#define APU_ENDCURVE 0x1000
|
||||
#define APU_APUTYPE_MASK 0x00f0
|
||||
#define APU_FILTERTYPE_MASK 0x000c
|
||||
#define APU_FILTERQ_MASK 0x0003
|
||||
|
||||
/* APU types */
|
||||
#define APU_APUTYPE_SHIFT 4
|
||||
|
||||
#define APUTYPE_INACTIVE 0
|
||||
#define APUTYPE_16BITLINEAR 1
|
||||
#define APUTYPE_16BITSTEREO 2
|
||||
#define APUTYPE_8BITLINEAR 3
|
||||
#define APUTYPE_8BITSTEREO 4
|
||||
#define APUTYPE_8BITDIFF 5
|
||||
#define APUTYPE_DIGITALDELAY 6
|
||||
#define APUTYPE_DUALTAP_READER 7
|
||||
#define APUTYPE_CORRELATOR 8
|
||||
#define APUTYPE_INPUTMIXER 9
|
||||
#define APUTYPE_WAVETABLE 10
|
||||
#define APUTYPE_RATECONV 11
|
||||
#define APUTYPE_16BITPINGPONG 12
|
||||
/* APU type 13 through 15 are reserved. */
|
||||
|
||||
/* Filter types */
|
||||
#define APU_FILTERTYPE_SHIFT 2
|
||||
|
||||
#define FILTERTYPE_2POLE_LOPASS 0
|
||||
#define FILTERTYPE_2POLE_BANDPASS 1
|
||||
#define FILTERTYPE_2POLE_HIPASS 2
|
||||
#define FILTERTYPE_1POLE_LOPASS 3
|
||||
#define FILTERTYPE_1POLE_HIPASS 4
|
||||
#define FILTERTYPE_PASSTHROUGH 5
|
||||
|
||||
/* Filter Q */
|
||||
#define APU_FILTERQ_SHIFT 0
|
||||
|
||||
#define FILTERQ_LESSQ 0
|
||||
#define FILTERQ_MOREQ 3
|
||||
|
||||
/* APU register 2 */
|
||||
#define APUREG_FREQ_LOBYTE 2
|
||||
#define APU_FREQ_LOBYTE_MASK 0xff00
|
||||
#define APU_plus6dB 0x0010
|
||||
|
||||
/* APU register 3 */
|
||||
#define APUREG_FREQ_HIWORD 3
|
||||
#define APU_FREQ_HIWORD_MASK 0x0fff
|
||||
|
||||
/* Frequency */
|
||||
#define APU_FREQ_LOBYTE_SHIFT 8
|
||||
#define APU_FREQ_HIWORD_SHIFT 0
|
||||
#define FREQ_Hz2DIV(freq) (((u_int64_t)(freq) << 16) / 48000)
|
||||
|
||||
/* APU register 4 */
|
||||
#define APUREG_WAVESPACE 4
|
||||
#define APU_64KPAGE_MASK 0xff00
|
||||
|
||||
/* 64KW (==128KB) Page */
|
||||
#define APU_64KPAGE_SHIFT 8
|
||||
|
||||
/* Wave Processor Wavespace Address */
|
||||
#define WPWA_MAX ((1 << 22) - 1)
|
||||
#define WPWA_STEREO (1 << 23)
|
||||
#define WPWA_USE_SYSMEM (1 << 22)
|
||||
|
||||
#define WPWA_WTBAR_SHIFT(wtsz) WPWA_WTBAR_SHIFT_##wtsz
|
||||
#define WPWA_WTBAR_SHIFT_1 15
|
||||
#define WPWA_WTBAR_SHIFT_2 16
|
||||
#define WPWA_WTBAR_SHIFT_4 17
|
||||
#define WPWA_WTBAR_SHIFT_8 18
|
||||
|
||||
#define WPWA_PCMBAR_SHIFT 20
|
||||
|
||||
/* APU register 5 - 7 */
|
||||
#define APUREG_CURPTR 5
|
||||
#define APUREG_ENDPTR 6
|
||||
#define APUREG_LOOPLEN 7
|
||||
|
||||
/* APU register 8 */
|
||||
#define APUREG_EFFECT_GAIN 8
|
||||
|
||||
/* Effect gain? */
|
||||
#define APUREG_EFFECT_GAIN_MASK 0x00ff
|
||||
|
||||
/* APU register 9 */
|
||||
#define APUREG_AMPLITUDE 9
|
||||
#define APU_AMPLITUDE_NOW_MASK 0xff00
|
||||
#define APU_AMPLITUDE_DEST_MASK 0x00ff
|
||||
|
||||
/* Amplitude now? */
|
||||
#define APU_AMPLITUDE_NOW_SHIFT 8
|
||||
|
||||
/* APU register 10 */
|
||||
#define APUREG_POSITION 10
|
||||
#define APU_RADIUS_MASK 0x00c0
|
||||
#define APU_PAN_MASK 0x003f
|
||||
|
||||
/* Radius control. */
|
||||
#define APU_RADIUS_SHIFT 6
|
||||
#define RADIUS_CENTERCIRCLE 0
|
||||
#define RADIUS_MIDDLE 1
|
||||
#define RADIUS_OUTSIDE 2
|
||||
|
||||
/* Polar pan. */
|
||||
#define APU_PAN_SHIFT 0
|
||||
#define PAN_RIGHT 0x00
|
||||
#define PAN_FRONT 0x08
|
||||
#define PAN_LEFT 0x10
|
||||
|
||||
/* Source routing. */
|
||||
#define APUREG_ROUTING 11
|
||||
#define APU_INVERT_POLARITY_B 0x8000
|
||||
#define APU_DATASRC_B_MASK 0x7f00
|
||||
#define APU_INVERT_POLARITY_A 0x0080
|
||||
#define APU_DATASRC_A_MASK 0x007f
|
||||
|
||||
#define APU_DATASRC_A_SHIFT 0
|
||||
#define APU_DATASRC_B_SHIFT 8
|
||||
|
||||
/* -----------------------------
|
||||
* Limits.
|
||||
*/
|
||||
#define WPWA_MAXADDR ((1 << 23) - 1)
|
||||
#define MAESTRO_MAXADDR ((1 << 28) - 1)
|
||||
|
||||
#endif /* MAESTRO_REG_H_INCLUDED */
|
||||
|
|
@ -6,14 +6,13 @@ SYSDIR?=${SRCTOP}/sys
|
|||
# Modules that include binary-only blobs of microcode should be selectable by
|
||||
# MK_SOURCELESS_UCODE option (see below).
|
||||
|
||||
SUBDIR= ad1816 als4000 atiixp cs4281 ${_csa} ${_ds1} emu10k1 emu10kx
|
||||
SUBDIR+= envy24 envy24ht es137x ess fm801 hda hdspe ich maestro
|
||||
SUBDIR= ad1816 als4000 atiixp cs4281 ${_csa} emu10k1 emu10kx
|
||||
SUBDIR+= envy24 envy24ht es137x ess fm801 hda hdspe ich
|
||||
SUBDIR+= ${_maestro3} neomagic sb16 sb8 sbc solo spicds t4dwave via8233
|
||||
SUBDIR+= via82c686 vibes driver uaudio
|
||||
|
||||
.if ${MK_SOURCELESS_UCODE} != "no"
|
||||
_csa= csa
|
||||
_ds1= ds1
|
||||
_maestro3= maestro3
|
||||
.endif
|
||||
|
||||
|
|
|
|||
|
|
@ -1,9 +0,0 @@
|
|||
# $FreeBSD$
|
||||
|
||||
.PATH: ${SRCTOP}/sys/dev/sound/pci
|
||||
|
||||
KMOD= snd_ds1
|
||||
SRCS= device_if.h bus_if.h pci_if.h
|
||||
SRCS+= ds1.c
|
||||
|
||||
.include <bsd.kmod.mk>
|
||||
|
|
@ -1,9 +0,0 @@
|
|||
# $FreeBSD$
|
||||
|
||||
.PATH: ${SRCTOP}/sys/dev/sound/pci
|
||||
|
||||
KMOD= snd_maestro
|
||||
SRCS= device_if.h bus_if.h pci_if.h
|
||||
SRCS+= maestro.c
|
||||
|
||||
.include <bsd.kmod.mk>
|
||||
Loading…
Reference in a new issue