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Add macros for the individual divisor bits as some MC146818A-compatible

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chips also use them for different purposes.
This commit is contained in:
Marius Strobl 2007-01-20 14:57:51 +00:00
parent 0c7d35d0b9
commit 8dbf0223f3
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=166149
1 changed files with 7 additions and 4 deletions
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11
sys/dev/mc146818/mc146818reg.h
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@ -82,6 +82,9 @@
#define MC_REGA_RSMASK 0x0f /* Interrupt rate select mask (see below) */ #define MC_REGA_RSMASK 0x0f /* Interrupt rate select mask (see below) */
#define MC_REGA_DVMASK 0x70 /* Divisor select mask (see below) */ #define MC_REGA_DVMASK 0x70 /* Divisor select mask (see below) */
#define MC_REGA_DV0 0x10 /* Divisor 0 */
#define MC_REGA_DV1 0x20 /* Divisor 1 */
#define MC_REGA_DV2 0x40 /* Divisor 2 */
#define MC_REGA_UIP 0x80 /* Update in progress; read only. */ #define MC_REGA_UIP 0x80 /* Update in progress; read only. */
#define MC_REGB 0xb /* Control register B */ #define MC_REGB 0xb /* Control register B */
@ -139,7 +142,7 @@
* Time base (divisor select) constants (Control register A) * Time base (divisor select) constants (Control register A)
*/ */
#define MC_BASE_4_MHz 0x00 /* 4MHz crystal */ #define MC_BASE_4_MHz 0x00 /* 4MHz crystal */
#define MC_BASE_1_MHz 0x10 /* 1MHz crystal */ #define MC_BASE_1_MHz MC_REGA_DV0 /* 1MHz crystal */
#define MC_BASE_32_KHz 0x20 /* 32KHz crystal */ #define MC_BASE_32_KHz MC_REGA_DV1 /* 32KHz crystal */
#define MC_BASE_NONE 0x60 /* actually, both of these reset */ #define MC_BASE_NONE (MC_REGA_DV2 | MC_REGA_DV1) /* actually also resets */
#define MC_BASE_RESET 0x70 #define MC_BASE_RESET (MC_REGA_DV2 | MC_REGA_DV1 | MC_REGA_DV0)