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Split out the arm64 EL2 exception vectors
These were originally in locore.S as they are only needed so we have a valid value to put into the vbar_el2 register. As these will soon be used by bhyve so move them to a new file as we already have with the EL1 exception vectors in exception.S. Obtained from: https://github.com/FreeBSD-UPB/freebsd-src (earlier version) Sponsored by: Innovate UK Sponsored by: The FreeBSD Foundation
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Andrew Turner
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2468c61958
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8a2adde1e4
65
sys/arm64/arm64/hyp_stub.S
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65
sys/arm64/arm64/hyp_stub.S
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@ -0,0 +1,65 @@
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/*
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* Copyright (c) 2017 Alexandru Elisei <alexandru.elisei@gmail.com>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <machine/asm.h>
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.macro vempty
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.align 7
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1: b 1b
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.endm
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/*
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* Install a new exception vector table with the base address supplied by the
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* parameter in register x0.
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*/
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.macro vector_stub_el1h_sync
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.align 7
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msr vbar_el2, x0
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ERET
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.endm
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.align 11
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.globl hyp_stub_vectors
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hyp_stub_vectors:
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vempty /* Synchronous EL2t */
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vempty /* IRQ EL2t */
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vempty /* FIQ EL2t */
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vempty /* SError EL2t */
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vempty /* Synchronous EL2h */
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vempty /* IRQ EL2h */
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vempty /* FIQ EL2h */
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vempty /* SError EL2h */
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vector_stub_el1h_sync /* Synchronous 64-bit EL1 */
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vempty /* IRQ 64-bit EL1 */
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vempty /* FIQ 64-bit EL1 */
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vempty /* SError 64-bit EL1 */
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vempty /* Synchronous 32-bit EL1 */
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vempty /* IRQ 32-bit EL1 */
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vempty /* FIQ 32-bit EL1 */
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vempty /* SError 32-bit EL1 */
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@ -291,8 +291,8 @@ LENTRY(drop_to_el1)
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msr cntvoff_el2, xzr
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/* Hypervisor trap functions */
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adrp x2, hyp_vectors
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add x2, x2, :lo12:hyp_vectors
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adrp x2, hyp_stub_vectors
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add x2, x2, :lo12:hyp_stub_vectors
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msr vbar_el2, x2
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/* Zero vttbr_el2 so a hypervisor can tell the host and guest apart */
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@ -326,32 +326,6 @@ LENTRY(drop_to_el1)
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.quad SCTLR_RES1
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LEND(drop_to_el1)
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#define VECT_EMPTY \
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.align 7; \
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1: b 1b
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.align 11
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hyp_vectors:
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VECT_EMPTY /* Synchronous EL2t */
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VECT_EMPTY /* IRQ EL2t */
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VECT_EMPTY /* FIQ EL2t */
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VECT_EMPTY /* Error EL2t */
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VECT_EMPTY /* Synchronous EL2h */
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VECT_EMPTY /* IRQ EL2h */
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VECT_EMPTY /* FIQ EL2h */
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VECT_EMPTY /* Error EL2h */
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VECT_EMPTY /* Synchronous 64-bit EL1 */
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VECT_EMPTY /* IRQ 64-bit EL1 */
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VECT_EMPTY /* FIQ 64-bit EL1 */
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VECT_EMPTY /* Error 64-bit EL1 */
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VECT_EMPTY /* Synchronous 32-bit EL1 */
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VECT_EMPTY /* IRQ 32-bit EL1 */
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VECT_EMPTY /* FIQ 32-bit EL1 */
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VECT_EMPTY /* Error 32-bit EL1 */
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/*
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* Get the delta between the physical address we were loaded to and the
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* virtual address we expect to run from. This is used when building the
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@ -51,6 +51,7 @@ arm64/arm64/gicv3_its.c optional intrng fdt
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arm64/arm64/gic_v3.c standard
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arm64/arm64/gic_v3_acpi.c optional acpi
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arm64/arm64/gic_v3_fdt.c optional fdt
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arm64/arm64/hyp_stub.S standard
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arm64/arm64/identcpu.c standard
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arm64/arm64/locore.S standard no-obj
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arm64/arm64/machdep.c standard
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