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Merge commit 8757ce490130 from llvm-project (by Simon Pilgrim):
[PowerPC] Replace PPCISD::VABSD cases with generic ISD::ABDU(X,Y) node
A move towards using the generic ISD::ABDU nodes on more backends
Also support ISD::ABDS for v4i32 types using the existing signbit flip trick
PowerPC has a select(icmp_ugt(x,y),sub(x,y),sub(y,x)) -> abdu(x,y) combine that I intend to move to DAGCombiner in a future patch.
The ABS(SUB(X,Y)) -> PPCISD::VABSD(X,Y,1) v4i32 combine wasn't legal (https://alive2.llvm.org/ce/z/jc2hLU) - so I've removed it, having already added the legal sub nsw tests equivalent.
Differential Revision: https://reviews.llvm.org/D142313
This fixes a "Wasn't expecting to be able to lower this!" fatal error
when compiling graphics/opencv for PowerPC.
Requested by: pkubaj
PR: 271047
MFC after: 1 month
This commit is contained in:
Dimitry Andric
parent
4da7282a18
commit
881fc20356
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@ -1299,6 +1299,11 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Legal);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal);
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setOperationAction(ISD::ABDU, MVT::v16i8, Legal);
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setOperationAction(ISD::ABDU, MVT::v8i16, Legal);
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setOperationAction(ISD::ABDU, MVT::v4i32, Legal);
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setOperationAction(ISD::ABDS, MVT::v4i32, Legal);
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}
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if (Subtarget.hasP10Vector()) {
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@ -1386,7 +1391,7 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
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}
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if (Subtarget.hasP9Altivec()) {
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setTargetDAGCombine({ISD::ABS, ISD::VSELECT});
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setTargetDAGCombine({ISD::VSELECT});
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}
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setLibcallName(RTLIB::LOG_F128, "logf128");
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@ -1743,7 +1748,6 @@ const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
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case PPCISD::RFEBB: return "PPCISD::RFEBB";
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case PPCISD::XXSWAPD: return "PPCISD::XXSWAPD";
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case PPCISD::SWAP_NO_CHAIN: return "PPCISD::SWAP_NO_CHAIN";
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case PPCISD::VABSD: return "PPCISD::VABSD";
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case PPCISD::BUILD_FP128: return "PPCISD::BUILD_FP128";
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case PPCISD::BUILD_SPE64: return "PPCISD::BUILD_SPE64";
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case PPCISD::EXTRACT_SPE: return "PPCISD::EXTRACT_SPE";
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@ -16008,8 +16012,6 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
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}
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case ISD::BUILD_VECTOR:
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return DAGCombineBuildVector(N, DCI);
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case ISD::ABS:
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return combineABS(N, DCI);
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case ISD::VSELECT:
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return combineVSelect(N, DCI);
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}
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@ -17437,24 +17439,6 @@ SDValue PPCTargetLowering::combineTRUNCATE(SDNode *N,
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SDLoc dl(N);
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SDValue Op0 = N->getOperand(0);
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// fold (truncate (abs (sub (zext a), (zext b)))) -> (vabsd a, b)
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if (Subtarget.hasP9Altivec() && Op0.getOpcode() == ISD::ABS) {
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EVT VT = N->getValueType(0);
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if (VT != MVT::v4i32 && VT != MVT::v8i16 && VT != MVT::v16i8)
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return SDValue();
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SDValue Sub = Op0.getOperand(0);
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if (Sub.getOpcode() == ISD::SUB) {
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SDValue SubOp0 = Sub.getOperand(0);
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SDValue SubOp1 = Sub.getOperand(1);
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if ((SubOp0.getOpcode() == ISD::ZERO_EXTEND) &&
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(SubOp1.getOpcode() == ISD::ZERO_EXTEND)) {
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return DCI.DAG.getNode(PPCISD::VABSD, dl, VT, SubOp0.getOperand(0),
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SubOp1.getOperand(0),
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DCI.DAG.getTargetConstant(0, dl, MVT::i32));
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}
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}
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}
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// Looking for a truncate of i128 to i64.
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if (Op0.getValueType() != MVT::i128 || N->getValueType(0) != MVT::i64)
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return SDValue();
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@ -17664,54 +17648,12 @@ isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const {
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return true;
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}
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// Transform (abs (sub (zext a), (zext b))) to (vabsd a b 0)
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// Transform (abs (sub (zext a), (zext_invec b))) to (vabsd a b 0)
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// Transform (abs (sub (zext_invec a), (zext_invec b))) to (vabsd a b 0)
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// Transform (abs (sub (zext_invec a), (zext b))) to (vabsd a b 0)
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// Transform (abs (sub a, b) to (vabsd a b 1)) if a & b of type v4i32
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SDValue PPCTargetLowering::combineABS(SDNode *N, DAGCombinerInfo &DCI) const {
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assert((N->getOpcode() == ISD::ABS) && "Need ABS node here");
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assert(Subtarget.hasP9Altivec() &&
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"Only combine this when P9 altivec supported!");
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EVT VT = N->getValueType(0);
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if (VT != MVT::v4i32 && VT != MVT::v8i16 && VT != MVT::v16i8)
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return SDValue();
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SelectionDAG &DAG = DCI.DAG;
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SDLoc dl(N);
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if (N->getOperand(0).getOpcode() == ISD::SUB) {
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// Even for signed integers, if it's known to be positive (as signed
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// integer) due to zero-extended inputs.
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unsigned SubOpcd0 = N->getOperand(0)->getOperand(0).getOpcode();
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unsigned SubOpcd1 = N->getOperand(0)->getOperand(1).getOpcode();
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if ((SubOpcd0 == ISD::ZERO_EXTEND ||
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SubOpcd0 == ISD::ZERO_EXTEND_VECTOR_INREG) &&
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(SubOpcd1 == ISD::ZERO_EXTEND ||
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SubOpcd1 == ISD::ZERO_EXTEND_VECTOR_INREG)) {
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return DAG.getNode(PPCISD::VABSD, dl, N->getOperand(0).getValueType(),
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N->getOperand(0)->getOperand(0),
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N->getOperand(0)->getOperand(1),
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DAG.getTargetConstant(0, dl, MVT::i32));
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}
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// For type v4i32, it can be optimized with xvnegsp + vabsduw
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if (N->getOperand(0).getValueType() == MVT::v4i32 &&
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N->getOperand(0).hasOneUse()) {
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return DAG.getNode(PPCISD::VABSD, dl, N->getOperand(0).getValueType(),
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N->getOperand(0)->getOperand(0),
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N->getOperand(0)->getOperand(1),
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DAG.getTargetConstant(1, dl, MVT::i32));
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}
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}
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return SDValue();
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}
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// For type v4i32/v8ii16/v16i8, transform
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// from (vselect (setcc a, b, setugt), (sub a, b), (sub b, a)) to (vabsd a, b)
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// from (vselect (setcc a, b, setuge), (sub a, b), (sub b, a)) to (vabsd a, b)
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// from (vselect (setcc a, b, setult), (sub b, a), (sub a, b)) to (vabsd a, b)
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// from (vselect (setcc a, b, setule), (sub b, a), (sub a, b)) to (vabsd a, b)
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// from (vselect (setcc a, b, setugt), (sub a, b), (sub b, a)) to (abdu a, b)
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// from (vselect (setcc a, b, setuge), (sub a, b), (sub b, a)) to (abdu a, b)
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// from (vselect (setcc a, b, setult), (sub b, a), (sub a, b)) to (abdu a, b)
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// from (vselect (setcc a, b, setule), (sub b, a), (sub a, b)) to (abdu a, b)
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// TODO: Move this to DAGCombiner?
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SDValue PPCTargetLowering::combineVSelect(SDNode *N,
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DAGCombinerInfo &DCI) const {
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assert((N->getOpcode() == ISD::VSELECT) && "Need VSELECT node here");
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@ -17762,9 +17704,8 @@ SDValue PPCTargetLowering::combineVSelect(SDNode *N,
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TrueOpnd.getOperand(1) == CmpOpnd2 &&
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FalseOpnd.getOperand(0) == CmpOpnd2 &&
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FalseOpnd.getOperand(1) == CmpOpnd1) {
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return DAG.getNode(PPCISD::VABSD, dl, N->getOperand(1).getValueType(),
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CmpOpnd1, CmpOpnd2,
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DAG.getTargetConstant(0, dl, MVT::i32));
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return DAG.getNode(ISD::ABDU, dl, N->getOperand(1).getValueType(), CmpOpnd1,
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CmpOpnd2, DAG.getTargetConstant(0, dl, MVT::i32));
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}
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return SDValue();
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@ -440,21 +440,6 @@ namespace llvm {
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/// and thereby have no chain.
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SWAP_NO_CHAIN,
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/// An SDNode for Power9 vector absolute value difference.
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/// operand #0 vector
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/// operand #1 vector
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/// operand #2 constant i32 0 or 1, to indicate whether needs to patch
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/// the most significant bit for signed i32
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///
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/// Power9 VABSD* instructions are designed to support unsigned integer
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/// vectors (byte/halfword/word), if we want to make use of them for signed
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/// integer vectors, we have to flip their sign bits first. To flip sign bit
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/// for byte/halfword integer vector would become inefficient, but for word
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/// integer vector, we can leverage XVNEGSP to make it efficiently. eg:
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/// abs(sub(a,b)) => VABSDUW(a+0x80000000, b+0x80000000)
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/// => VABSDUW((XVNEGSP a), (XVNEGSP b))
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VABSD,
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/// FP_EXTEND_HALF(VECTOR, IDX) - Custom extend upper (IDX=0) half or
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/// lower (IDX=1) half of v4f32 to v2f64.
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FP_EXTEND_HALF,
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@ -1422,7 +1407,6 @@ namespace llvm {
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SDValue combineFMALike(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue combineTRUNCATE(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue combineSetCC(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue combineABS(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue combineVSelect(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue combineVectorShuffle(ShuffleVectorSDNode *SVN,
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SelectionDAG &DAG) const;
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@ -76,9 +76,6 @@ def SDT_PPCxxswapd : SDTypeProfile<1, 1, [
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def SDTVecConv : SDTypeProfile<1, 2, [
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SDTCisVec<0>, SDTCisVec<1>, SDTCisPtrTy<2>
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]>;
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def SDTVabsd : SDTypeProfile<1, 3, [
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SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisVT<3, i32>
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]>;
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def SDT_PPCld_vec_be : SDTypeProfile<1, 1, [
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SDTCisVec<0>, SDTCisPtrTy<1>
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]>;
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@ -105,7 +102,6 @@ def PPCmtvsrz : SDNode<"PPCISD::MTVSRZ", SDTUnaryOp, []>;
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def PPCsvec2fp : SDNode<"PPCISD::SINT_VEC_TO_FP", SDTVecConv, []>;
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def PPCuvec2fp: SDNode<"PPCISD::UINT_VEC_TO_FP", SDTVecConv, []>;
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def PPCswapNoChain : SDNode<"PPCISD::SWAP_NO_CHAIN", SDT_PPCxxswapd>;
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def PPCvabsd : SDNode<"PPCISD::VABSD", SDTVabsd, []>;
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def PPCfpexth : SDNode<"PPCISD::FP_EXTEND_HALF", SDT_PPCfpexth, []>;
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def PPCldvsxlh : SDNode<"PPCISD::LD_VSX_LH", SDT_PPCldvsxlh,
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@ -4808,20 +4804,23 @@ def : Pat<(f128 (uint_to_fp (i32 (PPCmfvsr f64:$src)))),
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// Any Power9 VSX subtarget that supports Power9 Altivec.
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let Predicates = [HasVSX, HasP9Altivec] in {
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// Put this P9Altivec related definition here since it's possible to be
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// selected to VSX instruction xvnegsp, avoid possible undef.
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def : Pat<(v4i32 (PPCvabsd v4i32:$A, v4i32:$B, (i32 0))),
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// Unsigned absolute-difference.
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def : Pat<(v4i32 (abdu v4i32:$A, v4i32:$B)),
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(v4i32 (VABSDUW $A, $B))>;
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def : Pat<(v8i16 (PPCvabsd v8i16:$A, v8i16:$B, (i32 0))),
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def : Pat<(v8i16 (abdu v8i16:$A, v8i16:$B)),
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(v8i16 (VABSDUH $A, $B))>;
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def : Pat<(v16i8 (PPCvabsd v16i8:$A, v16i8:$B, (i32 0))),
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def : Pat<(v16i8 (abdu v16i8:$A, v16i8:$B)),
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(v16i8 (VABSDUB $A, $B))>;
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// As PPCVABSD description, the last operand indicates whether do the
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// sign bit flip.
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def : Pat<(v4i32 (PPCvabsd v4i32:$A, v4i32:$B, (i32 1))),
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// Signed absolute-difference.
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// Power9 VABSD* instructions are designed to support unsigned integer
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// vectors (byte/halfword/word), if we want to make use of them for signed
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// integer vectors, we have to flip their sign bits first. To flip sign bit
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// for byte/halfword integer vector would become inefficient, but for word
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// integer vector, we can leverage XVNEGSP to make it efficiently.
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def : Pat<(v4i32 (abds v4i32:$A, v4i32:$B)),
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(v4i32 (VABSDUW (XVNEGSP $A), (XVNEGSP $B)))>;
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} // HasVSX, HasP9Altivec
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