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powerpc: Implement atomic_(f)cmpset_ for short and char
| This adds two implementations for each atomic_fcmpset_ and atomic_cmpset_ short and char functions, selectable at compile time for the target architecture. By default, it uses a generic shift-and-mask to perform atomic updates to sub-components of 32-bit words from <sys/_atomic_subword.h>. However, if ISA_206_ATOMICS is defined it uses the ll/sc instructions for halfword and bytes, introduced in PowerISA 2.06. These instructions are supported by all IBM processors from POWER7 on, as well as the Freescale/NXP e6500 core. Although the e5500 and e500mc both implement PowerISA 2.06 they do not implement these instructions. As part of this, clean up the atomic_(f)cmpset_acq and _rel wrappers, by using macros to reduce code duplication. ISA_206_ATOMICS requires clang or newer binutils (2.20 or later). Differential Revision: https://reviews.freebsd.org/D21682
This commit is contained in:
Justin Hibbits
parent
cb49ec5431
commit
84046d16eb
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=353296
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@ -560,6 +560,56 @@ atomic_store_rel_long(volatile u_long *addr, u_long val)
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* two values are equal, update the value of *p with newval. Returns
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* zero if the compare failed, nonzero otherwise.
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*/
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#ifdef ISA_206_ATOMICS
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static __inline int
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atomic_cmpset_char(volatile u_char *p, u_char cmpval, u_char newval)
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{
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int ret;
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__asm __volatile (
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"1:\tlbarx %0, 0, %2\n\t" /* load old value */
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"cmplw %3, %0\n\t" /* compare */
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"bne- 2f\n\t" /* exit if not equal */
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"stbcx. %4, 0, %2\n\t" /* attempt to store */
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"bne- 1b\n\t" /* spin if failed */
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"li %0, 1\n\t" /* success - retval = 1 */
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"b 3f\n\t" /* we've succeeded */
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"2:\n\t"
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"stbcx. %0, 0, %2\n\t" /* clear reservation (74xx) */
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"li %0, 0\n\t" /* failure - retval = 0 */
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"3:\n\t"
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: "=&r" (ret), "=m" (*p)
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: "r" (p), "r" (cmpval), "r" (newval), "m" (*p)
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: "cr0", "memory");
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return (ret);
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}
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static __inline int
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atomic_cmpset_short(volatile u_short *p, u_short cmpval, u_short newval)
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{
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int ret;
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__asm __volatile (
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"1:\tlharx %0, 0, %2\n\t" /* load old value */
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"cmplw %3, %0\n\t" /* compare */
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"bne- 2f\n\t" /* exit if not equal */
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"sthcx. %4, 0, %2\n\t" /* attempt to store */
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"bne- 1b\n\t" /* spin if failed */
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"li %0, 1\n\t" /* success - retval = 1 */
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"b 3f\n\t" /* we've succeeded */
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"2:\n\t"
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"sthcx. %0, 0, %2\n\t" /* clear reservation (74xx) */
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"li %0, 0\n\t" /* failure - retval = 0 */
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"3:\n\t"
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: "=&r" (ret), "=m" (*p)
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: "r" (p), "r" (cmpval), "r" (newval), "m" (*p)
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: "cr0", "memory");
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return (ret);
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}
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#endif
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static __inline int
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atomic_cmpset_int(volatile u_int* p, u_int cmpval, u_int newval)
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{
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@ -618,39 +668,36 @@ atomic_cmpset_long(volatile u_long* p, u_long cmpval, u_long newval)
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return (ret);
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}
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static __inline int
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atomic_cmpset_acq_int(volatile u_int *p, u_int cmpval, u_int newval)
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{
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int retval;
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#define ATOMIC_CMPSET_ACQ_REL(type) \
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static __inline int \
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atomic_cmpset_acq_##type(volatile u_##type *p, \
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u_##type cmpval, u_##type newval)\
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{\
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u_##type retval; \
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retval = atomic_cmpset_##type(p, cmpval, newval);\
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__ATOMIC_ACQ();\
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return (retval);\
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}\
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static __inline int \
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atomic_cmpset_rel_##type(volatile u_##type *p, \
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u_##type cmpval, u_##type newval)\
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{\
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__ATOMIC_ACQ();\
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return (atomic_cmpset_##type(p, cmpval, newval));\
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}\
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struct hack
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retval = atomic_cmpset_int(p, cmpval, newval);
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__ATOMIC_ACQ();
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return (retval);
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}
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ATOMIC_CMPSET_ACQ_REL(int);
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ATOMIC_CMPSET_ACQ_REL(long);
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static __inline int
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atomic_cmpset_rel_int(volatile u_int *p, u_int cmpval, u_int newval)
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{
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__ATOMIC_REL();
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return (atomic_cmpset_int(p, cmpval, newval));
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}
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static __inline int
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atomic_cmpset_acq_long(volatile u_long *p, u_long cmpval, u_long newval)
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{
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u_long retval;
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#define atomic_cmpset_8 atomic_cmpset_char
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#define atomic_cmpset_acq_8 atomic_cmpset_acq_char
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#define atomic_cmpset_rel_8 atomic_cmpset_rel_char
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retval = atomic_cmpset_long(p, cmpval, newval);
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__ATOMIC_ACQ();
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return (retval);
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}
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static __inline int
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atomic_cmpset_rel_long(volatile u_long *p, u_long cmpval, u_long newval)
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{
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__ATOMIC_REL();
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return (atomic_cmpset_long(p, cmpval, newval));
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}
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#define atomic_cmpset_16 atomic_cmpset_short
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#define atomic_cmpset_acq_16 atomic_cmpset_acq_short
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#define atomic_cmpset_rel_16 atomic_cmpset_rel_short
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#define atomic_cmpset_32 atomic_cmpset_int
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#define atomic_cmpset_acq_32 atomic_cmpset_acq_int
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@ -676,13 +723,65 @@ atomic_cmpset_rel_long(volatile u_long *p, u_long cmpval, u_long newval)
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* zero if the compare failed and sets *cmpval to the read value from *p,
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* nonzero otherwise.
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*/
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#ifdef ISA_206_ATOMICS
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static __inline int
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atomic_fcmpset_char(volatile u_char *p, u_char *cmpval, u_char newval)
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{
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int ret;
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__asm __volatile (
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"lbarx %0, 0, %3\n\t" /* load old value */
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"cmplw %4, %0\n\t" /* compare */
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"bne- 1f\n\t" /* exit if not equal */
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"stbcx. %5, 0, %3\n\t" /* attempt to store */
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"bne- 1f\n\t" /* exit if failed */
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"li %0, 1\n\t" /* success - retval = 1 */
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"b 2f\n\t" /* we've succeeded */
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"1:\n\t"
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"stbcx. %0, 0, %3\n\t" /* clear reservation (74xx) */
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"stwx %0, 0, %7\n\t"
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"li %0, 0\n\t" /* failure - retval = 0 */
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"2:\n\t"
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: "=&r" (ret), "=m" (*p), "=m" (*cmpval)
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: "r" (p), "r" (*cmpval), "r" (newval), "m" (*p), "r"(cmpval)
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: "cr0", "memory");
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return (ret);
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}
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static __inline int
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atomic_fcmpset_short(volatile u_short *p, u_short *cmpval, u_short newval)
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{
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int ret;
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__asm __volatile (
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"lharx %0, 0, %3\n\t" /* load old value */
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"cmplw %4, %0\n\t" /* compare */
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"bne- 1f\n\t" /* exit if not equal */
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"sthcx. %5, 0, %3\n\t" /* attempt to store */
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"bne- 1f\n\t" /* exit if failed */
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"li %0, 1\n\t" /* success - retval = 1 */
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"b 2f\n\t" /* we've succeeded */
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"1:\n\t"
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"sthcx. %0, 0, %3\n\t" /* clear reservation (74xx) */
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"stwx %0, 0, %7\n\t"
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"li %0, 0\n\t" /* failure - retval = 0 */
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"2:\n\t"
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: "=&r" (ret), "=m" (*p), "=m" (*cmpval)
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: "r" (p), "r" (*cmpval), "r" (newval), "m" (*p), "r"(cmpval)
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: "cr0", "memory");
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return (ret);
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}
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#endif /* ISA_206_ATOMICS */
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static __inline int
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atomic_fcmpset_int(volatile u_int *p, u_int *cmpval, u_int newval)
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{
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int ret;
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__asm __volatile (
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"lwarx %0, 0, %3\n\t" /* load old value */
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"lwarx %0, 0, %3\n\t" /* load old value */
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"cmplw %4, %0\n\t" /* compare */
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"bne- 1f\n\t" /* exit if not equal */
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"stwcx. %5, 0, %3\n\t" /* attempt to store */
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@ -707,12 +806,12 @@ atomic_fcmpset_long(volatile u_long *p, u_long *cmpval, u_long newval)
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__asm __volatile (
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#ifdef __powerpc64__
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"ldarx %0, 0, %3\n\t" /* load old value */
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"ldarx %0, 0, %3\n\t" /* load old value */
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"cmpld %4, %0\n\t" /* compare */
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"bne- 1f\n\t" /* exit if not equal */
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"stdcx. %5, 0, %3\n\t" /* attempt to store */
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#else
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"lwarx %0, 0, %3\n\t" /* load old value */
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"lwarx %0, 0, %3\n\t" /* load old value */
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"cmplw %4, %0\n\t" /* compare */
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"bne- 1f\n\t" /* exit if not equal */
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"stwcx. %5, 0, %3\n\t" /* attempt to store */
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@ -737,39 +836,35 @@ atomic_fcmpset_long(volatile u_long *p, u_long *cmpval, u_long newval)
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return (ret);
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}
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static __inline int
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atomic_fcmpset_acq_int(volatile u_int *p, u_int *cmpval, u_int newval)
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{
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int retval;
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#define ATOMIC_FCMPSET_ACQ_REL(type) \
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static __inline int \
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atomic_fcmpset_acq_##type(volatile u_##type *p, \
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u_##type *cmpval, u_##type newval)\
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{\
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u_##type retval; \
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retval = atomic_fcmpset_##type(p, cmpval, newval);\
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__ATOMIC_ACQ();\
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return (retval);\
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}\
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static __inline int \
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atomic_fcmpset_rel_##type(volatile u_##type *p, \
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u_##type *cmpval, u_##type newval)\
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{\
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__ATOMIC_REL();\
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return (atomic_fcmpset_##type(p, cmpval, newval));\
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}\
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struct hack
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retval = atomic_fcmpset_int(p, cmpval, newval);
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__ATOMIC_ACQ();
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return (retval);
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}
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ATOMIC_FCMPSET_ACQ_REL(int);
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ATOMIC_FCMPSET_ACQ_REL(long);
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static __inline int
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atomic_fcmpset_rel_int(volatile u_int *p, u_int *cmpval, u_int newval)
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{
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__ATOMIC_REL();
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return (atomic_fcmpset_int(p, cmpval, newval));
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}
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#define atomic_fcmpset_8 atomic_fcmpset_char
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#define atomic_fcmpset_acq_8 atomic_fcmpset_acq_char
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#define atomic_fcmpset_rel_8 atomic_fcmpset_rel_char
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static __inline int
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atomic_fcmpset_acq_long(volatile u_long *p, u_long *cmpval, u_long newval)
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{
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u_long retval;
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retval = atomic_fcmpset_long(p, cmpval, newval);
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__ATOMIC_ACQ();
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return (retval);
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}
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static __inline int
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atomic_fcmpset_rel_long(volatile u_long *p, u_long *cmpval, u_long newval)
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{
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__ATOMIC_REL();
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return (atomic_fcmpset_long(p, cmpval, newval));
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}
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#define atomic_fcmpset_16 atomic_fcmpset_short
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#define atomic_fcmpset_acq_16 atomic_fcmpset_acq_short
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#define atomic_fcmpset_rel_16 atomic_fcmpset_rel_short
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#define atomic_fcmpset_32 atomic_fcmpset_int
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#define atomic_fcmpset_acq_32 atomic_fcmpset_acq_int
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@ -857,9 +952,6 @@ atomic_swap_64(volatile u_long *p, u_long v)
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#define atomic_swap_ptr(p,v) atomic_swap_32((volatile u_int *)(p), v)
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#endif
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#undef __ATOMIC_REL
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#undef __ATOMIC_ACQ
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static __inline void
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atomic_thread_fence_acq(void)
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{
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@ -888,4 +980,18 @@ atomic_thread_fence_seq_cst(void)
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__asm __volatile("sync" : : : "memory");
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}
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#ifndef ISA_206_ATOMICS
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#include <sys/_atomic_subword.h>
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#endif
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/* These need sys/_atomic_subword.h on non-ISA-2.06-atomic platforms. */
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ATOMIC_CMPSET_ACQ_REL(char);
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ATOMIC_CMPSET_ACQ_REL(short);
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ATOMIC_FCMPSET_ACQ_REL(char);
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ATOMIC_FCMPSET_ACQ_REL(short);
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#undef __ATOMIC_REL
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#undef __ATOMIC_ACQ
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#endif /* ! _MACHINE_ATOMIC_H_ */
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