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https://github.com/freebsd/freebsd-src
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Change region 4 to be part of the kernel. This serves 2 purposes:
1. The PBVM is in region 4, so if we want to make use of it, we need region 4 freed up. 2. Region 4 and above cannot be represented by an off_t by virtue of that type being signed. This is problematic for truss(1), ktrace(1) and other such programs.
This commit is contained in:
parent
ef89d04f13
commit
7c9eed5c4e
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=219808
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@ -260,7 +260,7 @@ db_backtrace(struct thread *td, struct pcb *pcb, int count)
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sym = db_search_symbol(ip, DB_STGY_ANY, &offset);
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db_symbol_values(sym, &name, NULL);
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db_printf("%s(", name);
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if (bsp >= IA64_RR_BASE(5)) {
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if (bsp >= VM_MAXUSER_ADDRESS) {
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for (i = 0; i < args; i++) {
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if ((bsp & 0x1ff) == 0x1f8)
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bsp += 8;
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@ -279,12 +279,12 @@ db_backtrace(struct thread *td, struct pcb *pcb, int count)
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if (error != ERESTART)
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continue;
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if (sp < IA64_RR_BASE(5))
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if (sp < VM_MAXUSER_ADDRESS)
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break;
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tf = (struct trapframe *)(sp + 16);
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if ((tf->tf_flags & FRAME_SYSCALL) != 0 ||
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tf->tf_special.iip < IA64_RR_BASE(5))
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tf->tf_special.iip < VM_MAXUSER_ADDRESS)
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break;
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/* XXX ask if we should unwind across the trapframe. */
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@ -177,7 +177,7 @@ gdb_cpu_query(void)
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* kernel stack address. See also ptrace_machdep().
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*/
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bspstore = kdb_frame->tf_special.bspstore;
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kstack = (bspstore >= IA64_RR_BASE(5)) ? (uint64_t*)bspstore :
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kstack = (bspstore >= VM_MAXUSER_ADDRESS) ? (uint64_t*)bspstore :
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(uint64_t*)(kdb_thread->td_kstack + (bspstore & 0x1ffUL));
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gdb_tx_begin('\0');
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gdb_tx_mem((void*)(kstack + slot), 8);
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@ -102,17 +102,11 @@ __FBSDID("$FreeBSD$");
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* We reserve region ID 0 for the kernel and allocate the remaining
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* IDs for user pmaps.
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*
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* Region 0..4
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* User virtually mapped
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*
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* Region 5
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* Kernel virtually mapped
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*
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* Region 6
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* Kernel physically mapped uncacheable
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*
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* Region 7
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* Kernel physically mapped cacheable
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* Region 0-3: User virtually mapped
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* Region 4: PBVM and special mappings
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* Region 5: Kernel virtual memory
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* Region 6: Direct-mapped uncacheable
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* Region 7: Direct-mapped cacheable
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*/
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/* XXX move to a header. */
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@ -346,9 +340,9 @@ pmap_bootstrap()
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* Setup RIDs. RIDs 0..7 are reserved for the kernel.
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*
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* We currently need at least 19 bits in the RID because PID_MAX
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* can only be encoded in 17 bits and we need RIDs for 5 regions
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* can only be encoded in 17 bits and we need RIDs for 4 regions
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* per process. With PID_MAX equalling 99999 this means that we
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* need to be able to encode 499995 (=5*PID_MAX).
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* need to be able to encode 399996 (=4*PID_MAX).
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* The Itanium processor only has 18 bits and the architected
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* minimum is exactly that. So, we cannot use a PID based scheme
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* in those cases. Enter pmap_ridmap...
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@ -390,7 +384,7 @@ pmap_bootstrap()
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*/
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ia64_kptdir = (void *)pmap_steal_memory(PAGE_SIZE);
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nkpt = 0;
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kernel_vm_end = VM_MIN_KERNEL_ADDRESS - VM_GATEWAY_SIZE;
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kernel_vm_end = VM_MIN_KERNEL_ADDRESS;
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for (i = 0; phys_avail[i+2]; i+= 2)
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;
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@ -451,16 +445,13 @@ pmap_bootstrap()
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* Initialize the kernel pmap (which is statically allocated).
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*/
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PMAP_LOCK_INIT(kernel_pmap);
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for (i = 0; i < 5; i++)
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for (i = 0; i < IA64_VM_MINKERN_REGION; i++)
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kernel_pmap->pm_rid[i] = 0;
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TAILQ_INIT(&kernel_pmap->pm_pvlist);
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PCPU_SET(md.current_pmap, kernel_pmap);
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/*
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* Region 5 is mapped via the vhpt.
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*/
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ia64_set_rr(IA64_RR_BASE(5),
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(5 << 8) | (PAGE_SHIFT << 2) | 1);
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/* Region 5 is mapped via the VHPT. */
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ia64_set_rr(IA64_RR_BASE(5), (5 << 8) | (PAGE_SHIFT << 2) | 1);
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/*
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* Region 6 is direct mapped UC and region 7 is direct mapped
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@ -678,7 +669,7 @@ pmap_pinit(struct pmap *pmap)
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int i;
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PMAP_LOCK_INIT(pmap);
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for (i = 0; i < 5; i++)
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for (i = 0; i < IA64_VM_MINKERN_REGION; i++)
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pmap->pm_rid[i] = pmap_allocate_rid();
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TAILQ_INIT(&pmap->pm_pvlist);
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bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
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@ -699,7 +690,7 @@ pmap_release(pmap_t pmap)
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{
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int i;
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for (i = 0; i < 5; i++)
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for (i = 0; i < IA64_VM_MINKERN_REGION; i++)
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if (pmap->pm_rid[i])
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pmap_free_rid(pmap->pm_rid[i]);
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PMAP_LOCK_DESTROY(pmap);
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@ -1221,7 +1212,7 @@ pmap_kextract(vm_offset_t va)
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struct ia64_lpte *pte;
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vm_offset_t gwpage;
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KASSERT(va >= IA64_RR_BASE(5), ("Must be kernel VA"));
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KASSERT(va >= VM_MAXUSER_ADDRESS, ("Must be kernel VA"));
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/* Regions 6 and 7 are direct mapped. */
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if (va >= IA64_RR_BASE(6))
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@ -1229,7 +1220,7 @@ pmap_kextract(vm_offset_t va)
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/* EPC gateway page? */
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gwpage = (vm_offset_t)ia64_get_k5();
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if (va >= gwpage && va < gwpage + VM_GATEWAY_SIZE)
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if (va >= gwpage && va < gwpage + PAGE_SIZE)
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return (IA64_RR_MASK((vm_offset_t)ia64_gateway_page));
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/* Bail out if the virtual address is beyond our limits. */
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@ -2285,12 +2276,12 @@ pmap_switch(pmap_t pm)
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if (prevpm == pm)
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goto out;
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if (pm == NULL) {
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for (i = 0; i < 5; i++) {
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for (i = 0; i < IA64_VM_MINKERN_REGION; i++) {
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ia64_set_rr(IA64_RR_BASE(i),
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(i << 8)|(PAGE_SHIFT << 2)|1);
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}
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} else {
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for (i = 0; i < 5; i++) {
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for (i = 0; i < IA64_VM_MINKERN_REGION; i++) {
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ia64_set_rr(IA64_RR_BASE(i),
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(pm->pm_rid[i] << 8)|(PAGE_SHIFT << 2)|1);
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}
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@ -50,6 +50,7 @@
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#include <sys/_mutex.h>
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#include <machine/atomic.h>
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#include <machine/pte.h>
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#include <machine/vmparam.h>
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#ifdef _KERNEL
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@ -75,7 +76,7 @@ struct md_page {
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struct pmap {
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struct mtx pm_mtx;
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TAILQ_HEAD(,pv_entry) pm_pvlist; /* list of mappings in pmap */
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uint32_t pm_rid[5]; /* base RID for pmap */
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uint32_t pm_rid[IA64_VM_MINKERN_REGION];
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struct pmap_statistics pm_stats; /* pmap statistics */
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};
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@ -41,12 +41,6 @@
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#ifndef _MACHINE_VMPARAM_H_
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#define _MACHINE_VMPARAM_H_
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/*
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* USRSTACK is the top (end) of the user stack. Immediately above the user
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* stack resides the syscall gateway page.
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*/
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#define USRSTACK VM_MAXUSER_ADDRESS
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/*
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* Virtual memory related constants, all in bytes
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*/
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#define VM_NRESERVLEVEL 0
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#endif
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#define IA64_VM_MINKERN_REGION 4
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/*
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* Manipulating region bits of an address.
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*/
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@ -138,7 +134,8 @@
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* to 0x1ffbffffffffffff. We define the top half of a region in terms of
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* this worst-case gap.
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*/
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#define IA64_REGION_TOP_HALF 0x1ffc000000000000
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#define IA64_REGION_GAP_START 0x0004000000000000
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#define IA64_REGION_GAP_EXTEND 0x1ffc000000000000
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/*
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* Page size of the identity mappings in region 7.
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#define IA64_ID_PAGE_SIZE (1<<(LOG2_ID_PAGE_SIZE))
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#define IA64_ID_PAGE_MASK (IA64_ID_PAGE_SIZE-1)
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#define IA64_BACKINGSTORE IA64_RR_BASE(4)
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/*
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* Parameters for Pre-Boot Virtual Memory (PBVM).
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* and wired into the CPU, but does not assume that the mapping covers the
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* whole of PBVM.
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*/
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#define IA64_PBVM_RR 4
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#define IA64_PBVM_RR IA64_VM_MINKERN_REGION
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#define IA64_PBVM_BASE \
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(IA64_RR_BASE(IA64_PBVM_RR) + IA64_REGION_TOP_HALF)
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(IA64_RR_BASE(IA64_PBVM_RR) + IA64_REGION_GAP_EXTEND)
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#define IA64_PBVM_PGTBL_MAXSZ 1048576
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#define IA64_PBVM_PGTBL \
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*/
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/* user/kernel map constants */
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#define VM_MIN_ADDRESS 0
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#define VM_MAXUSER_ADDRESS IA64_RR_BASE(5)
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#define VM_GATEWAY_SIZE PAGE_SIZE
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#define VM_MIN_KERNEL_ADDRESS (VM_MAXUSER_ADDRESS + VM_GATEWAY_SIZE)
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#define VM_MAX_KERNEL_ADDRESS (IA64_RR_BASE(6) - 1)
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#define VM_MIN_ADDRESS 0
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#define VM_MAXUSER_ADDRESS IA64_RR_BASE(IA64_VM_MINKERN_REGION)
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#define VM_MIN_KERNEL_ADDRESS IA64_RR_BASE(IA64_VM_MINKERN_REGION + 1)
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#define VM_MAX_KERNEL_ADDRESS (IA64_RR_BASE(IA64_VM_MINKERN_REGION + 2) - 1)
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#define VM_MAX_ADDRESS ~0UL
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#define KERNBASE VM_MAXUSER_ADDRESS
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/*
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* USRSTACK is the top (end) of the user stack. Immediately above the user
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* stack resides the syscall gateway page.
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*/
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#define USRSTACK VM_MAXUSER_ADDRESS
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#define IA64_BACKINGSTORE (USRSTACK - (2 * MAXSSIZ) - PAGE_SIZE)
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/* virtual sizes (bytes) for various kernel submaps */
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#ifndef VM_KMEM_SIZE
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#define VM_KMEM_SIZE (12 * 1024 * 1024)
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