mirror of
https://github.com/freebsd/freebsd-src
synced 2024-10-19 06:44:31 +00:00
Add 64 bit support to nlge, and additional fixes
- 64 bit fixes for ifnlge.c - Use m_nextpkt to save mbuf vaddr on 64 bit, we cannot store the 64 bit vaddr in the 40bit freeback field. - remove unused code and unnecessary variables. - use xlr_io_mmio macro instead of adding io base address - rewrite GPIO related code to fixup nlge using xlr_write_reg and DELAY - support for engg boards major num 11 and 12 - add xlr_paddr_lw() to load 32bit value from physical address, fix inline assembly - style fixes
This commit is contained in:
Jayachandran C.
parent
e29560acd7
commit
75e70f56a2
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=212896
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@ -381,8 +381,6 @@ nlna_attach(device_t dev)
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#ifdef DEBUG
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dump_board_info(&xlr_board_info);
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#endif
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block_info->baseaddr += DEFAULT_XLR_IO_BASE;
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/* Initialize nlna state in softc structure */
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sc = nlna_sc_init(dev, block_info);
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@ -621,21 +619,15 @@ nlge_msgring_handler(int bucket, int size, int code, int stid,
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{
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struct nlna_softc *na_sc;
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struct nlge_softc *sc;
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struct ifnet *ifp;
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struct ifnet *ifp;
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struct mbuf *m;
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vm_paddr_t phys_addr;
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unsigned long addr;
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uint32_t length;
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int ctrl;
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int cpu;
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int tx_error;
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int port;
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int vcpu;
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int is_p2p;
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cpu = xlr_core_id();
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vcpu = (cpu << 2) + xlr_thr_id();
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addr = 0;
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is_p2p = 0;
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tx_error = 0;
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length = (msg->msg0 >> 40) & 0x3fff;
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@ -667,7 +659,13 @@ nlge_msgring_handler(int bucket, int size, int code, int stid,
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if (is_p2p) {
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release_tx_desc(phys_addr);
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} else {
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m_freem((struct mbuf *)(uintptr_t)phys_addr);
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#ifdef __mips64
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m = (struct mbuf *)(uintptr_t)xlr_paddr_ld(phys_addr);
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m->m_nextpkt = NULL;
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#else
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m = (struct mbuf *)(uintptr_t)phys_addr;
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#endif
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m_freem(m);
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}
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NLGE_LOCK(sc);
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if (ifp->if_drv_flags & IFF_DRV_OACTIVE){
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@ -687,7 +685,7 @@ nlge_msgring_handler(int bucket, int size, int code, int stid,
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nlge_rx(sc, phys_addr, length);
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nlna_submit_rx_free_desc(na_sc, 1); /* return free descr to NA */
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} else {
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printf("[%s]: unrecognized ctrl=%d!\n", __FUNCTION__, ctrl);
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printf("[%s]: unrecognized ctrl=%d!\n", __func__, ctrl);
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}
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}
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@ -801,8 +799,8 @@ nlge_rx(struct nlge_softc *sc, vm_paddr_t paddr, int len)
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m = (struct mbuf *)(intptr_t)tm;
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if (mag != 0xf00bad) {
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/* somebody else's packet. Error - FIXME in intialization */
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printf("cpu %d: *ERROR* Not my packet paddr %llx\n",
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xlr_core_id(), (uint64_t) paddr);
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printf("cpu %d: *ERROR* Not my packet paddr %jx\n",
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xlr_core_id(), (uintmax_t)paddr);
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return;
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}
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@ -882,7 +880,7 @@ nlna_sc_init(device_t dev, struct xlr_gmac_block_t *blk)
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sc = device_get_softc(dev);
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memset(sc, 0, sizeof(*sc));
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sc->nlna_dev = dev;
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sc->base = (xlr_reg_t *) blk->baseaddr;
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sc->base = xlr_io_mmio(blk->baseaddr);
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sc->rfrbucket = blk->station_rfr;
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sc->station_id = blk->station_id;
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sc->na_type = blk->type;
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@ -1302,10 +1300,7 @@ nlna_reset_ports(struct nlna_softc *sc, struct xlr_gmac_block_t *blk)
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/* Refer Section 13.9.3 in the PRM for the reset sequence */
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for (i = 0; i < sc->num_ports; i++) {
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uint32_t base = (uint32_t)DEFAULT_XLR_IO_BASE;
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base += blk->gmac_port[i].base_addr;
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addr = (xlr_reg_t *) base;
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addr = xlr_io_mmio(blk->gmac_port[i].base_addr);
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/* 1. Reset RxEnable in MAC_CONFIG */
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switch (sc->mac_type) {
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@ -1359,10 +1354,7 @@ nlna_disable_ports(struct nlna_softc *sc)
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blk = device_get_ivars(sc->nlna_dev);
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for (i = 0; i < sc->num_ports; i++) {
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uint32_t base = (uint32_t)DEFAULT_XLR_IO_BASE;
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base += blk->gmac_port[i].base_addr;
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addr = (xlr_reg_t *) base;
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addr = xlr_io_mmio(blk->gmac_port[i].base_addr);
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nlge_port_disable(i, addr, blk->gmac_port[i].type);
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}
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}
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@ -1473,7 +1465,6 @@ static void
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nlge_sgmii_init(struct nlge_softc *sc)
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{
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xlr_reg_t *mmio_gpio;
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int i;
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int phy;
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if (sc->port_type != XLR_SGMII)
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@ -1491,12 +1482,26 @@ nlge_sgmii_init(struct nlge_softc *sc)
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nlge_mii_write_internal(sc->serdes_addr, 26, 9, 0x0000);
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nlge_mii_write_internal(sc->serdes_addr, 26,10, 0x0000);
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for(i=0;i<10000000;i++){} /* delay */
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/* program GPIO values for serdes init parameters */
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mmio_gpio = (xlr_reg_t *) (DEFAULT_XLR_IO_BASE + XLR_IO_GPIO_OFFSET);
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mmio_gpio[0x20] = 0x7e6802;
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mmio_gpio[0x10] = 0x7104;
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for(i=0;i<100000000;i++){}
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DELAY(100);
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mmio_gpio = xlr_io_mmio(XLR_IO_GPIO_OFFSET);
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xlr_write_reg(mmio_gpio, 0x20, 0x7e6802);
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xlr_write_reg(mmio_gpio, 0x10, 0x7104);
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DELAY(100);
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/*
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* This kludge is needed to setup serdes (?) clock correctly on some
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* XLS boards
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*/
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if ((xlr_boot1_info.board_major_version == RMI_XLR_BOARD_ARIZONA_XI ||
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xlr_boot1_info.board_major_version == RMI_XLR_BOARD_ARIZONA_XII) &&
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xlr_boot1_info.board_minor_version == 4) {
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/* use 125 Mhz instead of 156.25Mhz ref clock */
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DELAY(100);
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xlr_write_reg(mmio_gpio, 0x10, 0x7103);
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xlr_write_reg(mmio_gpio, 0x21, 0x7103);
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DELAY(100);
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}
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/* enable autoneg - more magic */
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phy = sc->phy_addr % 4 + 27;
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@ -1888,14 +1893,14 @@ prepare_fmn_message(struct nlge_softc *sc, struct msgrng_msg *fmn_msg,
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struct mbuf *m;
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struct nlge_tx_desc *p2p;
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uint64_t *cur_p2d;
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uint64_t fbpaddr;
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vm_offset_t buf;
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vm_paddr_t paddr;
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int msg_sz, p2p_sz, is_p2p;
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int len, frag_sz;
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int msg_sz, p2p_sz, len, frag_sz;
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/* Num entries per FMN msg is 4 for XLR/XLS */
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const int FMN_SZ = sizeof(*fmn_msg) / sizeof(uint64_t);
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msg_sz = p2p_sz = is_p2p = 0;
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msg_sz = p2p_sz = 0;
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p2p = NULL;
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cur_p2d = &fmn_msg->msg0;
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@ -1916,10 +1921,9 @@ prepare_fmn_message(struct nlge_softc *sc, struct msgrng_msg *fmn_msg,
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p2p->frag[XLR_MAX_TX_FRAGS] =
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(uint64_t)(vm_offset_t)p2p;
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cur_p2d = &p2p->frag[0];
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is_p2p = 1;
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} else if (msg_sz == (FMN_SZ - 2 + XLR_MAX_TX_FRAGS)) {
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uma_zfree(nl_tx_desc_zone, p2p);
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return 1;
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return (1);
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}
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paddr = vtophys(buf);
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frag_sz = PAGE_SIZE - (buf & PAGE_MASK);
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@ -1928,7 +1932,7 @@ prepare_fmn_message(struct nlge_softc *sc, struct msgrng_msg *fmn_msg,
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*cur_p2d++ = (127ULL << 54) | ((uint64_t)frag_sz << 40)
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| paddr;
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msg_sz++;
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if (is_p2p)
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if (p2p != NULL)
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p2p_sz++;
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len -= frag_sz;
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buf += frag_sz;
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@ -1938,15 +1942,28 @@ prepare_fmn_message(struct nlge_softc *sc, struct msgrng_msg *fmn_msg,
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if (msg_sz == 0) {
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printf("Zero-length mbuf chain ??\n");
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*n_entries = msg_sz ;
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return 0;
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return (0);
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}
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cur_p2d[-1] |= (1ULL << 63); /* set eop in most-recent p2d */
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*cur_p2d = (1ULL << 63) | ((uint64_t)fb_stn_id << 54) |
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(vm_offset_t) mbuf_chain; /* XXX: fix 64 bit */
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/* set eop in most-recent p2d */
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cur_p2d[-1] |= (1ULL << 63);
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#ifdef __mips64
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/*
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* On n64, we cannot store our mbuf pointer(64 bit) in the freeback
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* message (40bit available), so we put the mbuf in m_nextpkt and
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* use the physical addr of that in freeback message.
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*/
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mbuf_chain->m_nextpkt = mbuf_chain;
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fbpaddr = vtophys(&mbuf_chain->m_nextpkt);
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#else
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/* Careful, don't sign extend when going to 64bit */
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fbpaddr = (uint64_t)(uintptr_t)mbuf_chain;
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#endif
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*cur_p2d = (1ULL << 63) | ((uint64_t)fb_stn_id << 54) | fbpaddr;
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*tx_desc = p2p;
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if (is_p2p) {
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if (p2p != NULL) {
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paddr = vtophys(p2p);
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p2p_sz++;
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fmn_msg->msg3 = (1ULL << 62) | ((uint64_t)fb_stn_id << 54) |
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@ -1965,9 +1982,7 @@ send_fmn_msg_tx(struct nlge_softc *sc, struct msgrng_msg *msg,
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{
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uint32_t msgrng_flags;
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int ret;
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#ifdef INVARIANTS
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int i = 0;
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#endif
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do {
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msgrng_flags = msgrng_access_enable();
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@ -1979,7 +1994,7 @@ send_fmn_msg_tx(struct nlge_softc *sc, struct msgrng_msg *msg,
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i++;
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} while (i < 100000);
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KASSERT(i < 100000, ("Too many credit fails in tx path\n"));
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device_printf(sc->nlge_dev, "Too many credit fails in tx path\n");
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return (1);
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}
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@ -2012,7 +2027,7 @@ get_buf(void)
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if ((m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR)) == NULL)
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return (NULL);
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m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
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m_adj(m_new, XLR_CACHELINE_SIZE - ((unsigned int)m_new->m_data & 0x1f));
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m_adj(m_new, XLR_CACHELINE_SIZE - ((uintptr_t)m_new->m_data & 0x1f));
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md = (uint64_t *)m_new->m_data;
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md[0] = (intptr_t)m_new; /* Back Ptr */
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md[1] = 0xf00bad;
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@ -2107,16 +2122,12 @@ nlge_set_port_attribs(struct nlge_softc *sc,
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{
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sc->instance = port_info->instance % 4; /* TBD: will not work for SPI-4 */
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sc->port_type = port_info->type;
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sc->base = (xlr_reg_t *) (port_info->base_addr +
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(uint32_t)DEFAULT_XLR_IO_BASE);
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sc->mii_base = (xlr_reg_t *) (port_info->mii_addr +
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(uint32_t)DEFAULT_XLR_IO_BASE);
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sc->base = xlr_io_mmio(port_info->base_addr);
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sc->mii_base = xlr_io_mmio(port_info->mii_addr);
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if (port_info->pcs_addr != 0)
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sc->pcs_addr = (xlr_reg_t *) (port_info->pcs_addr +
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(uint32_t)DEFAULT_XLR_IO_BASE);
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sc->pcs_addr = xlr_io_mmio(port_info->pcs_addr);
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if (port_info->serdes_addr != 0)
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sc->serdes_addr = (xlr_reg_t *) (port_info->serdes_addr +
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(uint32_t)DEFAULT_XLR_IO_BASE);
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sc->serdes_addr = xlr_io_mmio(port_info->serdes_addr);
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sc->phy_addr = port_info->phy_addr;
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PDEBUG("Port%d: base=%p, mii_base=%p, phy_addr=%d\n", sc->id, sc->base,
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@ -418,6 +418,14 @@ xlr_ldaddwu(unsigned int value, unsigned int *addr)
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}
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#if defined(__mips_n64)
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static __inline uint32_t
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xlr_paddr_lw(uint64_t paddr)
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{
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paddr |= 0x9800000000000000ULL;
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return (*(uint32_t *)(uintptr_t)paddr);
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}
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static __inline uint64_t
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xlr_paddr_ld(uint64_t paddr)
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{
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@ -427,6 +435,23 @@ xlr_paddr_ld(uint64_t paddr)
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}
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#elif defined(__mips_n32)
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static __inline uint32_t
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xlr_paddr_lw(uint32_t paddr)
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{
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uint32_t val;
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paddr |= 0x9800000000000000ULL;
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__asm__ __volatile__(
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".set push \n\t"
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".set mips64 \n\t"
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"lw %0, 0(%1) \n\t"
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".set pop \n"
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: "=r"(val)
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: "r"(paddr));
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return (val);
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}
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static __inline uint64_t
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xlr_paddr_ld(uint64_t paddr)
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{
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@ -443,8 +468,33 @@ xlr_paddr_ld(uint64_t paddr)
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return (val);
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}
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#else
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#else /* o32 compilation */
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static __inline uint32_t
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xlr_paddr_lw(uint64_t paddr)
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{
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uint32_t addrh, addrl;
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uint32_t val;
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addrh = 0x98000000 | (paddr >> 32);
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addrl = paddr & 0xffffffff;
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__asm__ __volatile__(
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".set push \n\t"
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".set mips64 \n\t"
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"dsll32 %1, %1, 0 \n\t"
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"dsll32 %2, %2, 0 \n\t" /* get rid of the */
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"dsrl32 %2, %2, 0 \n\t" /* sign extend */
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"or %0, %1, %2 \n\t"
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"lw %0, 0(%0) \n\t"
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".set pop \n"
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: "=&r"(val)
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: "r"(addrh), "r"(addrl));
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return (val);
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}
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static __inline uint64_t
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xlr_paddr_ld(uint64_t paddr)
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{
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uint32_t addrh, addrl;
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@ -454,15 +504,15 @@ xlr_paddr_ld(uint64_t paddr)
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addrl = paddr & 0xffffffff;
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__asm__ __volatile__(
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".set push \n\t"
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".set mips64 \n\t"
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"dsll32 %2, %2, 0 \n\t"
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"dsll32 %3, %3, 0 \n\t" /* get rid of the */
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"dsrl32 %3, %3, 0 \n\t" /* sign extend */
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"or %2, %2, %3 \n\t"
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"lw %0, 0(%2) \n\t"
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"lw %1, 4(%2) \n\t"
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".set pop \n"
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".set push \n\t"
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".set mips64 \n\t"
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"dsll32 %2, %2, 0 \n\t"
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"dsll32 %3, %3, 0 \n\t" /* get rid of the */
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"dsrl32 %3, %3, 0 \n\t" /* sign extend */
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"or %0, %2, %3 \n\t"
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"lw %1, 4(%0) \n\t"
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"lw %0, 0(%0) \n\t"
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".set pop \n"
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: "=&r"(valh), "=r"(vall)
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: "r"(addrh), "r"(addrl));
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@ -485,7 +535,13 @@ static __inline void
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xlr_restore_kx(uint32_t sr)
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{
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}
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#else
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#else /* !defined(__mips_n64) && !defined(__mips_n32) */
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/*
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* o32 compilation, we will disable interrupts and enable
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* the KX bit so that we can use XKPHYS to access any 40bit
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* physical address
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*/
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static __inline uint32_t
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xlr_enable_kx(void)
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{
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@ -501,7 +557,7 @@ xlr_restore_kx(uint32_t sr)
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mips_wr_status(sr);
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}
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#endif
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#endif /* defined(__mips_n64) || defined(__mips_n32) */
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/* for cpuid to hardware thread id mapping */
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extern uint32_t xlr_hw_thread_mask;
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Reference in a new issue