mirror of
https://github.com/freebsd/freebsd-src
synced 2024-10-19 06:44:31 +00:00
Import Cavium's FreeBSD port, or the Octeon specific pieces, verbatim.
Yes, this puts things in the wrong place, doesn't compile and is woefully incomplete. However, it will allow us to more easily track against the upstream sources without needing to import the entire Cavium tree under vendor. This port is based on FreeBSD 7.0 as of April 2007 and the pre-import MIPS tree (aka mips2), so much work is necessary here.
This commit is contained in:
Warner Losh
parent
fdf7155886
commit
75c1942047
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/projects/mips/; revision=194140
13
sys/mips/conf/OCTEON.hints
Normal file
13
sys/mips/conf/OCTEON.hints
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
# /*
|
||||
# * This product includes software developed by the University of
|
||||
|
||||
# * California, Berkeley and its contributors."
|
||||
# */
|
||||
# device.hints
|
||||
hw.uart.console="io:0x1"
|
||||
hint.obio.0.at="nexus"
|
||||
hint.obio.0.maddr="0x1"
|
||||
hint.obio.0.flags="0x1"
|
||||
hint.uart.0.at="obio"
|
||||
hint.uart.0.maddr="0x1"
|
||||
hint.uart.0.flags="0x1"
|
||||
83
sys/mips/conf/OCTEON32
Normal file
83
sys/mips/conf/OCTEON32
Normal file
|
|
@ -0,0 +1,83 @@
|
|||
# QEMU -- Generic kernel configuration file for FreeBSD/mips
|
||||
#
|
||||
# For more information on this file, please read the handbook section on
|
||||
# Kernel Configuration Files:
|
||||
#
|
||||
# http://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html
|
||||
#
|
||||
# The handbook is also available locally in /usr/share/doc/handbook
|
||||
# if you've installed the doc distribution, otherwise always see the
|
||||
# FreeBSD World Wide Web server (http://www.FreeBSD.org/) for the
|
||||
# latest information.
|
||||
#
|
||||
# An exhaustive list of options and more detailed explanations of the
|
||||
# device lines is also present in the ../../conf/NOTES and NOTES files.
|
||||
# If you are in doubt as to the purpose or necessity of a line, check first
|
||||
# in NOTES.
|
||||
#
|
||||
# $FreeBSD$
|
||||
|
||||
machine mips
|
||||
cpu CPU_MIPS4KC
|
||||
ident CAVIUM
|
||||
|
||||
#makeoptions ARCH_FLAGS=-march=mips32
|
||||
|
||||
# Don't build any modules yet.
|
||||
makeoptions MODULES_OVERRIDE=""
|
||||
|
||||
options KERNVIRTADDR=0x80100000
|
||||
include "../mips4k/octeon32/std.octeon32"
|
||||
|
||||
hints "OCTEON.hints" #Default places to look for devices.
|
||||
|
||||
makeoptions DEBUG=-g #Build kernel with gdb(1) debug symbols
|
||||
|
||||
options DDB
|
||||
options KDB
|
||||
|
||||
options SCHED_4BSD #4BSD scheduler
|
||||
options INET #InterNETworking
|
||||
options NFSCLIENT #Network Filesystem Client
|
||||
#options NFS_ROOT #NFS usable as /, requires NFSCLIENT
|
||||
options PSEUDOFS #Pseudo-filesystem framework
|
||||
options _KPOSIX_PRIORITY_SCHEDULING #Posix P1003_1B real-time extensions
|
||||
#options ROOTDEVNAME=\"ufs:ad0s1a\" # Original
|
||||
options NO_SWAPPING
|
||||
|
||||
|
||||
options FFS #Berkeley Fast Filesystem
|
||||
options SOFTUPDATES #Enable FFS soft updates support
|
||||
options UFS_ACL #Support for access control lists
|
||||
options UFS_DIRHASH #Improve performance on big directories
|
||||
|
||||
|
||||
# Debugging for use in -current
|
||||
options INVARIANTS #Enable calls of extra sanity checking
|
||||
options INVARIANT_SUPPORT #Extra sanity checks of internal structures, required by INVARIANTS
|
||||
#options WITNESS #Enable checks to detect deadlocks and cycles
|
||||
#options WITNESS_SKIPSPIN #Don't run witness on spinlocks for speed
|
||||
|
||||
device genclock
|
||||
device loop
|
||||
device ether
|
||||
device md
|
||||
device mem
|
||||
device uart
|
||||
device uart_oct16550
|
||||
device rgmii
|
||||
#options VERBOSE_SYSINIT
|
||||
|
||||
|
||||
#
|
||||
# Use the following for Compact Flash file-system
|
||||
device cf
|
||||
options ROOTDEVNAME = \"ufs:cf0s2\" # Unmask if compact flash is needed as RFS
|
||||
|
||||
#
|
||||
# Use the following for RFS in mem-device
|
||||
#options MD_ROOT
|
||||
#options ROOTDEVNAME = \"ufs:md0\"
|
||||
|
||||
#options MD_ROOT_SIZE = 21264
|
||||
options SMP
|
||||
143
sys/mips/mips4k/octeon32/asm_octeon.S
Normal file
143
sys/mips/mips4k/octeon32/asm_octeon.S
Normal file
|
|
@ -0,0 +1,143 @@
|
|||
|
||||
#include <machine/asm.h>
|
||||
#include <machine/cache_r4k.h>
|
||||
#include <machine/cpuregs.h>
|
||||
#include <machine/param.h>
|
||||
#include <machine/pte.h>
|
||||
|
||||
#include "assym.s"
|
||||
|
||||
|
||||
|
||||
#define CPU_DISABLE_INTERRUPTS(reg, reg2, reg3) \
|
||||
mfc0 reg, MIPS_COP_0_STATUS; \
|
||||
nop; \
|
||||
move reg3, reg; \
|
||||
li reg2, ~MIPS_SR_INT_IE; \
|
||||
and reg, reg2, reg; \
|
||||
mtc0 reg, MIPS_COP_0_STATUS; \
|
||||
COP0_SYNC
|
||||
|
||||
|
||||
|
||||
#define CPU_ENABLE_INTERRUPTS(reg, reg3) \
|
||||
mfc0 reg, MIPS_COP_0_STATUS; \
|
||||
nop; \
|
||||
or reg, reg, reg3; \
|
||||
mtc0 reg, MIPS_COP_0_STATUS; \
|
||||
COP0_SYNC
|
||||
|
||||
|
||||
#define PUSHR(reg) \
|
||||
addiu sp,sp,-16 ; \
|
||||
sd reg, 8(sp) ; \
|
||||
nop ;
|
||||
|
||||
#define POPR(reg) \
|
||||
ld reg, 8(sp) ; \
|
||||
addiu sp,sp,16 ; \
|
||||
nop ;
|
||||
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* octeon_ciu_get_interrupt_reg_addr
|
||||
*
|
||||
* Given Int-X, En-X combination, return the CIU Interrupt Enable Register addr
|
||||
* a0 = ciu Int-X: 0/1
|
||||
* a1 = ciu EN-0: 0/1
|
||||
*/
|
||||
LEAF(octeon_ciu_get_interrupt_reg_addr)
|
||||
.set noreorder
|
||||
.set mips3
|
||||
|
||||
beqz a0, ciu_get_interrupt_reg_addr_Int_0
|
||||
nop
|
||||
|
||||
ciu_get_interrupt_reg_addr_Int_1:
|
||||
beqz a1, ciu_get_interrupt_reg_addr_Int_1_En_0
|
||||
nop
|
||||
|
||||
ciu_get_interrupt_reg_addr_Int_1_En1:
|
||||
li a0, OCTEON_CIU_ADDR_HI
|
||||
dsll32 a0, a0, 0
|
||||
nop
|
||||
ori a0, OCTEON_CIU_EN1_INT1_LO
|
||||
j ciu_get_interrupt_reg_addr_ret
|
||||
nop
|
||||
|
||||
ciu_get_interrupt_reg_addr_Int_1_En_0:
|
||||
li a0, OCTEON_CIU_ADDR_HI
|
||||
dsll32 a0, a0, 0
|
||||
nop
|
||||
ori a0, OCTEON_CIU_EN0_INT1_LO
|
||||
j ciu_get_interrupt_reg_addr_ret
|
||||
nop
|
||||
|
||||
ciu_get_interrupt_reg_addr_Int_0:
|
||||
beqz a1, ciu_get_interrupt_reg_addr_Int_0_En_0
|
||||
nop
|
||||
|
||||
ciu_get_interrupt_reg_addr_Int_0_En_1:
|
||||
li a0, OCTEON_CIU_ADDR_HI
|
||||
dsll32 a0, a0, 0
|
||||
nop
|
||||
ori a0, OCTEON_CIU_EN1_INT0_LO
|
||||
j ciu_get_interrupt_reg_addr_ret
|
||||
nop
|
||||
|
||||
ciu_get_interrupt_reg_addr_Int_0_En_0:
|
||||
li a0, OCTEON_CIU_ADDR_HI
|
||||
dsll32 a0, a0, 0
|
||||
nop
|
||||
ori a0, OCTEON_CIU_EN0_INT0_LO
|
||||
|
||||
|
||||
ciu_get_interrupt_reg_addr_ret:
|
||||
j ra
|
||||
nop
|
||||
|
||||
.set mips0
|
||||
.set reorder
|
||||
END(octeon_ciu_get_interrupt_reg_addr)
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* octeon_ciu_mask_all_interrupts
|
||||
*
|
||||
* a0 = ciu Interrupt-X: 0/1
|
||||
* a1 = ciu Enable-X: 0/1
|
||||
*/
|
||||
LEAF(octeon_ciu_mask_all_interrupts)
|
||||
.set noreorder
|
||||
.set mips3
|
||||
|
||||
PUSHR(ra)
|
||||
PUSHR(s0)
|
||||
|
||||
move t0, a0
|
||||
move t1, a1
|
||||
li a0, MIPS_SR_INT_IE
|
||||
CPU_DISABLE_INTERRUPTS(a2, a1, s0)
|
||||
move a0, t0
|
||||
move t1, a1
|
||||
jal octeon_ciu_get_interrupt_reg_addr
|
||||
nop
|
||||
ld a2, 0(a0) # Dummy read
|
||||
nop
|
||||
move a2, zero # Clear all
|
||||
sd a2, 0(a0) # Write new Enable bits
|
||||
nop
|
||||
CPU_ENABLE_INTERRUPTS(a2, s0)
|
||||
|
||||
POPR(s0)
|
||||
POPR(ra)
|
||||
j ra # Return
|
||||
nop # (bd slot)
|
||||
|
||||
.set mips0
|
||||
.set reorder
|
||||
END(octeon_ciu_mask_all_interrupts)
|
||||
|
||||
21
sys/mips/mips4k/octeon32/files.octeon32
Normal file
21
sys/mips/mips4k/octeon32/files.octeon32
Normal file
|
|
@ -0,0 +1,21 @@
|
|||
# /*
|
||||
# * This product includes software developed by the University of
|
||||
# * California, Berkeley and its contributors."
|
||||
# */
|
||||
# $FreeBSD$
|
||||
# Octeon Support Files
|
||||
#
|
||||
mips/mips4k/octeon32/obio.c optional uart
|
||||
mips/mips4k/octeon32/uart_cpu_octeonusart.c optional uart
|
||||
mips/mips4k/octeon32/uart_bus_octeonusart.c optional uart
|
||||
dev/uart/uart_dev_oct16550.c optional uart
|
||||
mips/mips/mp_machdep.c optional smp
|
||||
mips/mips4k/octeon32/octeon_machdep.c standard
|
||||
|
||||
dev/flash/octeon_ebt3000_cf.c optional cf
|
||||
|
||||
dev/le/octeon_fau.c optional rgmii
|
||||
dev/le/octeon_fpa.c optional rgmii
|
||||
dev/le/octeon_ipd.c optional rgmii
|
||||
dev/le/octeon_pko.c optional rgmii
|
||||
dev/le/octeon_rgmx.c optional rgmii
|
||||
185
sys/mips/mips4k/octeon32/obio.c
Normal file
185
sys/mips/mips4k/octeon32/obio.c
Normal file
|
|
@ -0,0 +1,185 @@
|
|||
/* $NetBSD: obio.c,v 1.11 2003/07/15 00:25:05 lukem Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2001, 2002, 2003 Wasabi Systems, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Written by Jason R. Thorpe for Wasabi Systems, Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed for the NetBSD Project by
|
||||
* Wasabi Systems, Inc.
|
||||
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
|
||||
* or promote products derived from this software without specific prior
|
||||
* written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* On-board device autoconfiguration support for Intel IQ80321
|
||||
* evaluation boards.
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD$");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/bus.h>
|
||||
#include <sys/kernel.h>
|
||||
#include <sys/module.h>
|
||||
#include <sys/rman.h>
|
||||
#include <sys/malloc.h>
|
||||
|
||||
#include <machine/bus.h>
|
||||
|
||||
#include <mips/mips4k/octeon32/octeonreg.h>
|
||||
#include <mips/mips4k/octeon32/obiovar.h>
|
||||
|
||||
int obio_probe(device_t);
|
||||
int obio_attach(device_t);
|
||||
|
||||
/*
|
||||
* We need only one obio.
|
||||
* Any other device hanging off of it, shouldn't cause multiple of
|
||||
* these to be found.
|
||||
*/
|
||||
static int have_one = 0;
|
||||
|
||||
int
|
||||
obio_probe(device_t dev)
|
||||
{
|
||||
if(!have_one)
|
||||
{
|
||||
have_one = 1;
|
||||
return 0;
|
||||
}
|
||||
else
|
||||
return (ENXIO);
|
||||
}
|
||||
|
||||
int
|
||||
obio_attach(device_t dev)
|
||||
{
|
||||
struct obio_softc *sc = device_get_softc(dev);
|
||||
|
||||
sc->oba_st = MIPS_BUS_SPACE_IO;
|
||||
sc->oba_addr = OCTEON_UART0ADR;
|
||||
sc->oba_size = 0x10000;
|
||||
sc->oba_rman.rm_type = RMAN_ARRAY;
|
||||
sc->oba_rman.rm_descr = "OBIO I/O";
|
||||
if (rman_init(&sc->oba_rman) != 0 ||
|
||||
rman_manage_region(&sc->oba_rman,
|
||||
sc->oba_addr, sc->oba_addr + sc->oba_size) != 0)
|
||||
panic("obio_attach: failed to set up I/O rman");
|
||||
sc->oba_irq_rman.rm_type = RMAN_ARRAY;
|
||||
sc->oba_irq_rman.rm_descr = "OBIO IRQ";
|
||||
|
||||
/*
|
||||
* This module is intended for UART purposes only and
|
||||
* it's IRQ is 0 corresponding to IP2.
|
||||
*/
|
||||
if (rman_init(&sc->oba_irq_rman) != 0 ||
|
||||
rman_manage_region(&sc->oba_irq_rman, 0, 0) != 0)
|
||||
panic("obio_attach: failed to set up IRQ rman");
|
||||
|
||||
device_add_child(dev, "uart", 1); /* Setup Uart-1 first. */
|
||||
device_add_child(dev, "uart", 0); /* Uart-0 next. So it is first in console list */
|
||||
bus_generic_probe(dev);
|
||||
bus_generic_attach(dev);
|
||||
return (0);
|
||||
}
|
||||
|
||||
static struct resource *
|
||||
obio_alloc_resource(device_t bus, device_t child, int type, int *rid,
|
||||
u_long start, u_long end, u_long count, u_int flags)
|
||||
{
|
||||
struct resource *rv;
|
||||
struct rman *rm;
|
||||
bus_space_tag_t bt = 0;
|
||||
bus_space_handle_t bh = 0;
|
||||
struct obio_softc *sc = device_get_softc(bus);
|
||||
|
||||
switch (type) {
|
||||
case SYS_RES_IRQ:
|
||||
rm = &sc->oba_irq_rman;
|
||||
break;
|
||||
case SYS_RES_MEMORY:
|
||||
return (NULL);
|
||||
case SYS_RES_IOPORT:
|
||||
rm = &sc->oba_rman;
|
||||
bt = sc->oba_st;
|
||||
bh = device_get_unit(child) ? OCTEON_UART1ADR : OCTEON_UART0ADR;
|
||||
start = bh;
|
||||
break;
|
||||
default:
|
||||
return (NULL);
|
||||
}
|
||||
|
||||
rv = rman_reserve_resource(rm, start, end, count, flags, child);
|
||||
if (rv == NULL) {
|
||||
return (NULL);
|
||||
}
|
||||
if (type == SYS_RES_IRQ) {
|
||||
return (rv);
|
||||
}
|
||||
rman_set_rid(rv, *rid);
|
||||
rman_set_bustag(rv, bt);
|
||||
rman_set_bushandle(rv, bh);
|
||||
|
||||
if (0) {
|
||||
if (bus_activate_resource(child, type, *rid, rv)) {
|
||||
rman_release_resource(rv);
|
||||
return (NULL);
|
||||
}
|
||||
}
|
||||
return (rv);
|
||||
|
||||
}
|
||||
|
||||
static int
|
||||
obio_activate_resource(device_t bus, device_t child, int type, int rid,
|
||||
struct resource *r)
|
||||
{
|
||||
return (0);
|
||||
}
|
||||
static device_method_t obio_methods[] = {
|
||||
DEVMETHOD(device_probe, obio_probe),
|
||||
DEVMETHOD(device_attach, obio_attach),
|
||||
|
||||
DEVMETHOD(bus_alloc_resource, obio_alloc_resource),
|
||||
DEVMETHOD(bus_activate_resource, obio_activate_resource),
|
||||
DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
|
||||
DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
|
||||
|
||||
{0, 0},
|
||||
};
|
||||
|
||||
static driver_t obio_driver = {
|
||||
"obio",
|
||||
obio_methods,
|
||||
sizeof(struct obio_softc),
|
||||
};
|
||||
static devclass_t obio_devclass;
|
||||
|
||||
DRIVER_MODULE(obio, nexus, obio_driver, obio_devclass, 0, 0);
|
||||
58
sys/mips/mips4k/octeon32/obiovar.h
Normal file
58
sys/mips/mips4k/octeon32/obiovar.h
Normal file
|
|
@ -0,0 +1,58 @@
|
|||
/* $NetBSD: obiovar.h,v 1.4 2003/06/16 17:40:53 thorpej Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2002, 2003 Wasabi Systems, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Written by Jason R. Thorpe for Wasabi Systems, Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed for the NetBSD Project by
|
||||
* Wasabi Systems, Inc.
|
||||
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
|
||||
* or promote products derived from this software without specific prior
|
||||
* written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _OCTEON_OBIOVAR_H_
|
||||
#define _OCTEON_OBIOVAR_H_
|
||||
|
||||
#include <sys/rman.h>
|
||||
|
||||
struct obio_softc {
|
||||
bus_space_tag_t oba_st; /* bus space tag */
|
||||
bus_addr_t oba_addr; /* address of device */
|
||||
bus_size_t oba_size; /* size of device */
|
||||
int oba_width; /* bus width */
|
||||
int oba_irq; /* XINT interrupt bit # */
|
||||
struct rman oba_rman;
|
||||
struct rman oba_irq_rman;
|
||||
|
||||
};
|
||||
extern struct bus_space obio_bs_tag;
|
||||
|
||||
#endif /* _OCTEON_OBIOVAR_H_ */
|
||||
914
sys/mips/mips4k/octeon32/octeon_machdep.c
Normal file
914
sys/mips/mips4k/octeon32/octeon_machdep.c
Normal file
|
|
@ -0,0 +1,914 @@
|
|||
/*-
|
||||
* Copyright (c) 2006 Wojciech A. Koszek <wkoszek@FreeBSD.org>
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD$");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
#include <machine/cpuregs.h>
|
||||
#include <machine/cpufunc.h>
|
||||
#include <mips/mips4k/octeon32/octeonreg.h>
|
||||
#include <machine/atomic.h>
|
||||
#include <machine/pcpu.h>
|
||||
|
||||
#if defined(__mips_n64)
|
||||
#define MAX_APP_DESC_ADDR 0xffffffffafffffff
|
||||
#else
|
||||
#define MAX_APP_DESC_ADDR 0xafffffff
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* Perform a board-level soft-reset.
|
||||
* Note that this is not emulated by gxemul.
|
||||
*/
|
||||
void octeon_reset (void)
|
||||
{
|
||||
void (*reset_func)(void) = (void (*)(void) )0x1fc00000;
|
||||
reset_func();
|
||||
}
|
||||
|
||||
|
||||
static inline uint32_t octeon_disable_interrupts (void)
|
||||
{
|
||||
uint32_t status_bits;
|
||||
|
||||
status_bits = mips_rd_status();
|
||||
mips_wr_status(status_bits & ~MIPS_SR_INT_IE);
|
||||
return (status_bits);
|
||||
}
|
||||
|
||||
|
||||
static inline void octeon_set_interrupts (uint32_t status_bits)
|
||||
{
|
||||
mips_wr_status(status_bits);
|
||||
}
|
||||
|
||||
|
||||
void octeon_led_write_char (int char_position, char val)
|
||||
{
|
||||
uint64_t ptr = (OCTEON_CHAR_LED_BASE_ADDR | 0xf8);
|
||||
|
||||
if (!octeon_board_real()) return;
|
||||
|
||||
char_position &= 0x7; /* only 8 chars */
|
||||
ptr += char_position;
|
||||
oct_write8_x8(ptr, val);
|
||||
}
|
||||
|
||||
void octeon_led_write_char0 (char val)
|
||||
{
|
||||
uint64_t ptr = (OCTEON_CHAR_LED_BASE_ADDR | 0xf8);
|
||||
|
||||
if (!octeon_board_real()) return;
|
||||
|
||||
oct_write8_x8(ptr, val);
|
||||
}
|
||||
|
||||
void octeon_led_write_hexchar (int char_position, char hexval)
|
||||
{
|
||||
uint64_t ptr = (OCTEON_CHAR_LED_BASE_ADDR | 0xf8);
|
||||
char char1, char2;
|
||||
|
||||
if (!octeon_board_real()) return;
|
||||
|
||||
char1 = (hexval >> 4) & 0x0f; char1 = (char1 < 10)?char1+'0':char1+'7';
|
||||
char2 = (hexval & 0x0f); char2 = (char2 < 10)?char2+'0':char2+'7';
|
||||
char_position &= 0x7; /* only 8 chars */
|
||||
if (char_position > 6) char_position = 6;
|
||||
ptr += char_position;
|
||||
oct_write8_x8(ptr, char1);
|
||||
ptr++;
|
||||
oct_write8_x8(ptr, char2);
|
||||
}
|
||||
|
||||
void octeon_led_write_string (const char *str)
|
||||
{
|
||||
uint64_t ptr = (OCTEON_CHAR_LED_BASE_ADDR | 0xf8);
|
||||
int i;
|
||||
|
||||
if (!octeon_board_real()) return;
|
||||
|
||||
for (i=0; i<8; i++, ptr++) {
|
||||
if (str && *str) {
|
||||
oct_write8_x8(ptr, *str++);
|
||||
} else {
|
||||
oct_write8_x8(ptr, ' ');
|
||||
}
|
||||
oct_read64(OCTEON_MIO_BOOT_BIST_STAT);
|
||||
}
|
||||
}
|
||||
|
||||
static char progress[8] = { '-', '/', '|', '\\', '-', '/', '|', '\\'};
|
||||
|
||||
void octeon_led_run_wheel (/*int count, */int *prog_count, int led_position)
|
||||
{
|
||||
if (!octeon_board_real()) return;
|
||||
|
||||
octeon_led_write_char(led_position, progress[*prog_count]);
|
||||
*prog_count += 1;
|
||||
*prog_count &= 0x7;
|
||||
}
|
||||
|
||||
#define LSR_DATAREADY 0x01 /* Data ready */
|
||||
#define LSR_THRE 0x20 /* Transmit holding register empty */
|
||||
#define LSR_TEMT 0x40 /* Transmitter Empty. THR, TSR & FIFO */
|
||||
#define USR_TXFIFO_NOTFULL 0x02 /* Uart TX FIFO Not full */
|
||||
|
||||
/*
|
||||
* octeon_uart_write_byte
|
||||
*
|
||||
* Put out a single byte off of uart port.
|
||||
*/
|
||||
|
||||
void octeon_uart_write_byte (int uart_index, uint8_t ch)
|
||||
{
|
||||
uint64_t val, val2;
|
||||
if ((uart_index < 0) || (uart_index > 1)) {
|
||||
return;
|
||||
}
|
||||
|
||||
while (1) {
|
||||
val = oct_read64(OCTEON_MIO_UART0_LSR + (uart_index * 0x400));
|
||||
val2 = oct_read64(OCTEON_MIO_UART0_USR + (uart_index * 0x400));
|
||||
if ((((uint8_t) val) & LSR_THRE) ||
|
||||
(((uint8_t) val2) & USR_TXFIFO_NOTFULL)) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* Write the byte */
|
||||
oct_write8(OCTEON_MIO_UART0_THR + (uart_index * 0x400), (uint64_t) ch);
|
||||
|
||||
/* Force Flush the IOBus */
|
||||
oct_read64(OCTEON_MIO_BOOT_BIST_STAT);
|
||||
}
|
||||
|
||||
|
||||
void octeon_uart_write_byte0 (uint8_t ch)
|
||||
{
|
||||
uint64_t val, val2;
|
||||
|
||||
while (1) {
|
||||
val = oct_read64(OCTEON_MIO_UART0_LSR);
|
||||
val2 = oct_read64(OCTEON_MIO_UART0_USR);
|
||||
if ((((uint8_t) val) & LSR_THRE) ||
|
||||
(((uint8_t) val2) & USR_TXFIFO_NOTFULL)) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* Write the byte */
|
||||
oct_write8(OCTEON_MIO_UART0_THR, (uint64_t) ch);
|
||||
|
||||
/* Force Flush the IOBus */
|
||||
oct_read64(OCTEON_MIO_BOOT_BIST_STAT);
|
||||
}
|
||||
|
||||
/*
|
||||
* octeon_uart_write_string
|
||||
*
|
||||
*/
|
||||
void octeon_uart_write_string (int uart_index, const char *str)
|
||||
{
|
||||
/* Just loop writing one byte at a time */
|
||||
|
||||
while (*str)
|
||||
{
|
||||
octeon_uart_write_byte(uart_index, *str);
|
||||
if (*str == '\n') {
|
||||
octeon_uart_write_byte(uart_index, '\r');
|
||||
}
|
||||
str++;
|
||||
}
|
||||
}
|
||||
|
||||
static char wstr[30];
|
||||
|
||||
void octeon_led_write_hex (uint32_t wl)
|
||||
{
|
||||
char nbuf[80];
|
||||
|
||||
sprintf(nbuf, "%X", wl);
|
||||
octeon_led_write_string(nbuf);
|
||||
}
|
||||
|
||||
|
||||
void octeon_uart_write_hex2 (uint32_t wl, uint32_t wh)
|
||||
{
|
||||
sprintf(wstr, "0x%X-0x%X ", wh, wl);
|
||||
octeon_uart_write_string(0, wstr);
|
||||
}
|
||||
|
||||
void octeon_uart_write_hex (uint32_t wl)
|
||||
{
|
||||
sprintf(wstr, " 0x%X ", wl);
|
||||
octeon_uart_write_string(0, wstr);
|
||||
}
|
||||
|
||||
|
||||
#define OCT_CONS_BUFLEN 200
|
||||
static char console_str_buff0[OCT_CONS_BUFLEN + 1];
|
||||
#include <machine/stdarg.h>
|
||||
|
||||
|
||||
//#define USE_KERN_SUBR_PRINTF
|
||||
|
||||
#ifndef USE_KERN_SUBR_PRINTF
|
||||
static int oct_printf (const char *fmt, va_list ap);
|
||||
#endif
|
||||
|
||||
int kern_cons_printf (const char *fmt, ...)
|
||||
{
|
||||
va_list ap;
|
||||
|
||||
va_start(ap, fmt);
|
||||
#ifndef USE_KERN_SUBR_PRINTF
|
||||
oct_printf(fmt, ap);
|
||||
#else
|
||||
ker_printf(fmt, ap);
|
||||
#endif
|
||||
va_end(ap);
|
||||
return (0);
|
||||
}
|
||||
|
||||
#ifndef USE_KERN_SUBR_PRINTF
|
||||
static int oct_printf (const char *fmt, va_list ap)
|
||||
{
|
||||
snprintf(console_str_buff0, OCT_CONS_BUFLEN, fmt, ap);
|
||||
octeon_uart_write_string(0, console_str_buff0);
|
||||
return (0);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
int console_printf (const char *fmt, ...)
|
||||
{
|
||||
va_list ap;
|
||||
|
||||
va_start(ap, fmt);
|
||||
sprintf(console_str_buff0, fmt, ap);
|
||||
va_end(ap);
|
||||
octeon_uart_write_string(0, console_str_buff0);
|
||||
return (0);
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* octeon_wait_uart_flush
|
||||
*/
|
||||
void octeon_wait_uart_flush (int uart_index, uint8_t ch)
|
||||
{
|
||||
uint64_t val;
|
||||
int64_t val3;
|
||||
uint32_t cpu_status_bits;
|
||||
|
||||
if ((uart_index < 0) || (uart_index > 1)) {
|
||||
return;
|
||||
}
|
||||
|
||||
cpu_status_bits = octeon_disable_interrupts();
|
||||
/* Force Flush the IOBus */
|
||||
oct_read64(OCTEON_MIO_BOOT_BIST_STAT);
|
||||
for (val3 = 0xfffffffff; val3 > 0; val3--) {
|
||||
val = oct_read64(OCTEON_MIO_UART0_LSR + (uart_index * 0x400));
|
||||
if (((uint8_t) val) & LSR_TEMT) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
octeon_set_interrupts(cpu_status_bits);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* octeon_debug_symbol
|
||||
*
|
||||
* Does nothing.
|
||||
* Used to mark the point for simulator to begin tracing
|
||||
*/
|
||||
void octeon_debug_symbol (void)
|
||||
{
|
||||
}
|
||||
|
||||
void octeon_ciu_stop_gtimer (int timer)
|
||||
{
|
||||
oct_write64(OCTEON_CIU_GENTIMER_ADDR(timer), 0ll);
|
||||
}
|
||||
|
||||
void octeon_ciu_start_gtimer (int timer, u_int one_shot, uint64_t time_cycles)
|
||||
{
|
||||
octeon_ciu_gentimer gentimer;
|
||||
|
||||
gentimer.word64 = 0;
|
||||
gentimer.bits.one_shot = one_shot;
|
||||
gentimer.bits.len = time_cycles - 1;
|
||||
oct_write64(OCTEON_CIU_GENTIMER_ADDR(timer), gentimer.word64);
|
||||
}
|
||||
|
||||
/*
|
||||
* octeon_ciu_reset
|
||||
*
|
||||
* Shutdown all CIU to IP2, IP3 mappings
|
||||
*/
|
||||
void octeon_ciu_reset (void)
|
||||
{
|
||||
|
||||
octeon_ciu_stop_gtimer(CIU_GENTIMER_NUM_0);
|
||||
octeon_ciu_stop_gtimer(CIU_GENTIMER_NUM_1);
|
||||
octeon_ciu_stop_gtimer(CIU_GENTIMER_NUM_2);
|
||||
octeon_ciu_stop_gtimer(CIU_GENTIMER_NUM_3);
|
||||
|
||||
ciu_disable_intr(CIU_THIS_CORE, CIU_INT_0, CIU_EN_0);
|
||||
ciu_disable_intr(CIU_THIS_CORE, CIU_INT_0, CIU_EN_1);
|
||||
ciu_disable_intr(CIU_THIS_CORE, CIU_INT_1, CIU_EN_0);
|
||||
ciu_disable_intr(CIU_THIS_CORE, CIU_INT_1, CIU_EN_1);
|
||||
|
||||
ciu_clear_int_summary(CIU_THIS_CORE, CIU_INT_0, CIU_EN_0, 0ll);
|
||||
ciu_clear_int_summary(CIU_THIS_CORE, CIU_INT_1, CIU_EN_0, 0ll);
|
||||
ciu_clear_int_summary(CIU_THIS_CORE, CIU_INT_1, CIU_EN_1, 0ll);
|
||||
}
|
||||
|
||||
/*
|
||||
* mips_disable_interrupt_controllers
|
||||
*
|
||||
* Disable interrupts in the CPU controller
|
||||
*/
|
||||
void mips_disable_interrupt_controls (void)
|
||||
{
|
||||
/*
|
||||
* Disable interrupts in CIU.
|
||||
*/
|
||||
octeon_ciu_reset();
|
||||
}
|
||||
|
||||
static uint64_t ciu_get_intr_sum_reg_addr(int core_num, int intx, int enx);
|
||||
|
||||
/*
|
||||
* ciu_get_intr_sum_reg_addr
|
||||
*/
|
||||
static uint64_t ciu_get_intr_sum_reg_addr (int core_num, int intx, int enx)
|
||||
{
|
||||
uint64_t ciu_intr_sum_reg_addr;
|
||||
|
||||
if (enx == CIU_EN_0) {
|
||||
ciu_intr_sum_reg_addr = OCTEON_CIU_SUMMARY_BASE_ADDR + (core_num * 0x10) +
|
||||
(intx * 0x8);
|
||||
} else {
|
||||
ciu_intr_sum_reg_addr = OCTEON_CIU_SUMMARY_INT1_ADDR;
|
||||
}
|
||||
|
||||
return (ciu_intr_sum_reg_addr);
|
||||
}
|
||||
|
||||
|
||||
static uint64_t ciu_get_intr_en_reg_addr(int core_num, int intx, int enx);
|
||||
|
||||
/*
|
||||
* ciu_get_intr_en_reg_addr
|
||||
*/
|
||||
static uint64_t ciu_get_intr_en_reg_addr (int core_num, int intx, int enx)
|
||||
{
|
||||
uint64_t ciu_intr_reg_addr;
|
||||
|
||||
|
||||
ciu_intr_reg_addr = OCTEON_CIU_ENABLE_BASE_ADDR + ((enx == 0) ? 0x0 : 0x8) +
|
||||
(intx * 0x10) + (core_num * 0x20);
|
||||
|
||||
return (ciu_intr_reg_addr);
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
uint64_t ciu_get_en_reg_addr_new (int corenum, int intx, int enx, int ciu_ip);
|
||||
|
||||
/*
|
||||
* ciu_get_intr_reg_addr
|
||||
*
|
||||
* 200 ---int0,en0 ip2
|
||||
* 208 ---int0,en1 ip2 ----> this is wrong... this is watchdog
|
||||
*
|
||||
* 210 ---int0,en0 ip3 --
|
||||
* 218 ---int0,en1 ip3 ----> same here.. .this is watchdog... right?
|
||||
*
|
||||
* 220 ---int1,en0 ip2
|
||||
* 228 ---int1,en1 ip2
|
||||
* 230 ---int1,en0 ip3 --
|
||||
* 238 ---int1,en1 ip3
|
||||
*
|
||||
*/
|
||||
uint64_t ciu_get_en_reg_addr_new (int corenum, int intx, int enx, int ciu_ip)
|
||||
{
|
||||
uint64_t ciu_intr_reg_addr = OCTEON_CIU_ENABLE_BASE_ADDR;
|
||||
|
||||
if (enx < CIU_EN_0 || enx > CIU_EN_1) {
|
||||
printf("%s: invalid enx value %d, should be %d or %d\n",
|
||||
__FUNCTION__, enx, CIU_EN_0, CIU_EN_1);
|
||||
return 0;
|
||||
}
|
||||
if (intx < CIU_INT_0 || intx > CIU_INT_1) {
|
||||
printf("%s: invalid intx value %d, should be %d or %d\n",
|
||||
__FUNCTION__, enx, CIU_INT_0, CIU_INT_1);
|
||||
return 0;
|
||||
}
|
||||
if (ciu_ip < CIU_MIPS_IP2 || ciu_ip > CIU_MIPS_IP3) {
|
||||
printf("%s: invalid ciu_ip value %d, should be %d or %d\n",
|
||||
__FUNCTION__, ciu_ip, CIU_MIPS_IP2, CIU_MIPS_IP3);
|
||||
return 0;
|
||||
}
|
||||
|
||||
ciu_intr_reg_addr += (enx * 0x8);
|
||||
ciu_intr_reg_addr += (ciu_ip * 0x10);
|
||||
ciu_intr_reg_addr += (intx * 0x20);
|
||||
|
||||
return (ciu_intr_reg_addr);
|
||||
}
|
||||
|
||||
/*
|
||||
* ciu_get_int_summary
|
||||
*/
|
||||
uint64_t ciu_get_int_summary (int core_num, int intx, int enx)
|
||||
{
|
||||
uint64_t ciu_intr_sum_reg_addr;
|
||||
|
||||
if (core_num == CIU_THIS_CORE) {
|
||||
core_num = octeon_get_core_num();
|
||||
}
|
||||
ciu_intr_sum_reg_addr = ciu_get_intr_sum_reg_addr(core_num, intx, enx);
|
||||
return (oct_read64(ciu_intr_sum_reg_addr));
|
||||
}
|
||||
|
||||
//#define DEBUG_CIU 1
|
||||
|
||||
#ifdef DEBUG_CIU
|
||||
#define DEBUG_CIU_SUM 1
|
||||
#define DEBUG_CIU_EN 1
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* ciu_clear_int_summary
|
||||
*/
|
||||
void ciu_clear_int_summary (int core_num, int intx, int enx, uint64_t write_bits)
|
||||
{
|
||||
uint32_t cpu_status_bits;
|
||||
uint64_t ciu_intr_sum_reg_addr;
|
||||
|
||||
//#define DEBUG_CIU_SUM 1
|
||||
|
||||
#ifdef DEBUG_CIU_SUM
|
||||
uint64_t ciu_intr_sum_bits;
|
||||
#endif
|
||||
|
||||
|
||||
if (core_num == CIU_THIS_CORE) {
|
||||
core_num = octeon_get_core_num();
|
||||
}
|
||||
|
||||
#ifdef DEBUG_CIU_SUM
|
||||
printf(" CIU: core %u clear sum IntX %u Enx %u Bits: 0x%llX\n",
|
||||
core_num, intx, enx, write_bits);
|
||||
#endif
|
||||
|
||||
cpu_status_bits = octeon_disable_interrupts();
|
||||
|
||||
ciu_intr_sum_reg_addr = ciu_get_intr_sum_reg_addr(core_num, intx, enx);
|
||||
|
||||
#ifdef DEBUG_CIU_SUM
|
||||
ciu_intr_sum_bits = oct_read64(ciu_intr_sum_reg_addr); /* unneeded dummy read */
|
||||
printf(" CIU: status: 0x%X reg_addr: 0x%llX Val: 0x%llX -> 0x%llX",
|
||||
cpu_status_bits, ciu_intr_sum_reg_addr, ciu_intr_sum_bits,
|
||||
ciu_intr_sum_bits | write_bits);
|
||||
#endif
|
||||
|
||||
oct_write64(ciu_intr_sum_reg_addr, write_bits);
|
||||
oct_read64(OCTEON_MIO_BOOT_BIST_STAT); /* Bus Barrier */
|
||||
|
||||
#ifdef DEBUG_CIU_SUM
|
||||
printf(" Readback: 0x%llX\n\n ", (uint64_t) oct_read64(ciu_intr_sum_reg_addr));
|
||||
#endif
|
||||
|
||||
octeon_set_interrupts(cpu_status_bits);
|
||||
}
|
||||
|
||||
/*
|
||||
* ciu_disable_intr
|
||||
*/
|
||||
void ciu_disable_intr (int core_num, int intx, int enx)
|
||||
{
|
||||
uint32_t cpu_status_bits;
|
||||
uint64_t ciu_intr_reg_addr;
|
||||
|
||||
if (core_num == CIU_THIS_CORE) {
|
||||
core_num = octeon_get_core_num();
|
||||
}
|
||||
|
||||
cpu_status_bits = octeon_disable_interrupts();
|
||||
|
||||
ciu_intr_reg_addr = ciu_get_intr_en_reg_addr(core_num, intx, enx);
|
||||
|
||||
oct_read64(ciu_intr_reg_addr); /* Dummy read */
|
||||
|
||||
oct_write64(ciu_intr_reg_addr, 0LL);
|
||||
oct_read64(OCTEON_MIO_BOOT_BIST_STAT); /* Bus Barrier */
|
||||
|
||||
octeon_set_interrupts(cpu_status_bits);
|
||||
}
|
||||
|
||||
void ciu_dump_interrutps_enabled (int core_num, int intx, int enx, int ciu_ip);
|
||||
void ciu_dump_interrutps_enabled (int core_num, int intx, int enx, int ciu_ip)
|
||||
{
|
||||
|
||||
uint64_t ciu_intr_reg_addr;
|
||||
uint64_t ciu_intr_bits;
|
||||
|
||||
if (core_num == CIU_THIS_CORE) {
|
||||
core_num = octeon_get_core_num();
|
||||
}
|
||||
|
||||
#ifndef OCTEON_SMP_1
|
||||
ciu_intr_reg_addr = ciu_get_intr_en_reg_addr(core_num, intx, enx);
|
||||
#else
|
||||
ciu_intr_reg_addr = ciu_get_en_reg_addr_new(core_num, intx, enx, ciu_ip);
|
||||
#endif
|
||||
|
||||
if (!ciu_intr_reg_addr) {
|
||||
printf("Bad call to %s\n", __FUNCTION__);
|
||||
while(1);
|
||||
return;
|
||||
}
|
||||
|
||||
ciu_intr_bits = oct_read64(ciu_intr_reg_addr);
|
||||
printf(" CIU core %d int: %d en: %d ip: %d Add: 0x%llX enabled: 0x%llX SR: %X\n",
|
||||
core_num, intx, enx, ciu_ip, ciu_intr_reg_addr, ciu_intr_bits, mips_rd_status());
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* ciu_enable_interrupts
|
||||
*/
|
||||
void ciu_enable_interrupts (int core_num, int intx, int enx, uint64_t set_these_interrupt_bits,
|
||||
int ciu_ip)
|
||||
{
|
||||
|
||||
uint32_t cpu_status_bits;
|
||||
uint64_t ciu_intr_reg_addr;
|
||||
uint64_t ciu_intr_bits;
|
||||
|
||||
if (core_num == CIU_THIS_CORE) {
|
||||
core_num = octeon_get_core_num();
|
||||
}
|
||||
|
||||
//#define DEBUG_CIU_EN 1
|
||||
|
||||
#ifdef DEBUG_CIU_EN
|
||||
printf(" CIU: core %u enabling Intx %u Enx %u IP %d Bits: 0x%llX\n",
|
||||
core_num, intx, enx, ciu_ip, set_these_interrupt_bits);
|
||||
#endif
|
||||
|
||||
cpu_status_bits = octeon_disable_interrupts();
|
||||
|
||||
#ifndef OCTEON_SMP_1
|
||||
ciu_intr_reg_addr = ciu_get_intr_en_reg_addr(core_num, intx, enx);
|
||||
#else
|
||||
ciu_intr_reg_addr = ciu_get_en_reg_addr_new(core_num, intx, enx, ciu_ip);
|
||||
#endif
|
||||
|
||||
if (!ciu_intr_reg_addr) {
|
||||
printf("Bad call to %s\n", __FUNCTION__);
|
||||
while(1);
|
||||
return;
|
||||
}
|
||||
|
||||
ciu_intr_bits = oct_read64(ciu_intr_reg_addr);
|
||||
|
||||
#ifdef DEBUG_CIU_EN
|
||||
printf(" CIU: status: 0x%X reg_addr: 0x%llX Val: 0x%llX -> 0x%llX",
|
||||
cpu_status_bits, ciu_intr_reg_addr, ciu_intr_bits, ciu_intr_bits | set_these_interrupt_bits);
|
||||
#endif
|
||||
ciu_intr_bits |= set_these_interrupt_bits;
|
||||
oct_write64(ciu_intr_reg_addr, ciu_intr_bits);
|
||||
#ifdef OCTEON_SMP
|
||||
mips_wbflush();
|
||||
#endif
|
||||
oct_read64(OCTEON_MIO_BOOT_BIST_STAT); /* Bus Barrier */
|
||||
|
||||
#ifdef DEBUG_CIU_EN
|
||||
printf(" Readback: 0x%llX\n\n ", (uint64_t) oct_read64(ciu_intr_reg_addr));
|
||||
#endif
|
||||
|
||||
octeon_set_interrupts(cpu_status_bits);
|
||||
}
|
||||
|
||||
|
||||
extern void mips_platform_init(void);
|
||||
|
||||
void mips_platform_init (void)
|
||||
{
|
||||
octeon_ciu_reset();
|
||||
octeon_uart_write_string(0, "\nPlatform Starting");
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*
|
||||
****************************************************************************************
|
||||
*
|
||||
* APP/BOOT DESCRIPTOR STUFF
|
||||
*
|
||||
****************************************************************************************
|
||||
*/
|
||||
|
||||
/* Define the struct that is initialized by the bootloader used by the
|
||||
* startup code.
|
||||
*
|
||||
* Copyright (c) 2004, 2005, 2006 Cavium Networks.
|
||||
*
|
||||
* The authors hereby grant permission to use, copy, modify, distribute,
|
||||
* and license this software and its documentation for any purpose, provided
|
||||
* that existing copyright notices are retained in all copies and that this
|
||||
* notice is included verbatim in any distributions. No written agreement,
|
||||
* license, or royalty fee is required for any of the authorized uses.
|
||||
* Modifications to this software may be copyrighted by their authors
|
||||
* and need not follow the licensing terms described here, provided that
|
||||
* the new terms are clearly indicated on the first page of each file where
|
||||
* they apply.
|
||||
*/
|
||||
|
||||
#define OCTEON_CURRENT_DESC_VERSION 6
|
||||
#define OCTEON_ARGV_MAX_ARGS (64)
|
||||
#define OCTOEN_SERIAL_LEN 20
|
||||
|
||||
|
||||
typedef struct {
|
||||
/* Start of block referenced by assembly code - do not change! */
|
||||
uint32_t desc_version;
|
||||
uint32_t desc_size;
|
||||
|
||||
uint64_t stack_top;
|
||||
uint64_t heap_base;
|
||||
uint64_t heap_end;
|
||||
uint64_t entry_point; /* Only used by bootloader */
|
||||
uint64_t desc_vaddr;
|
||||
/* End of This block referenced by assembly code - do not change! */
|
||||
|
||||
uint32_t exception_base_addr;
|
||||
uint32_t stack_size;
|
||||
uint32_t heap_size;
|
||||
uint32_t argc; /* Argc count for application */
|
||||
uint32_t argv[OCTEON_ARGV_MAX_ARGS];
|
||||
uint32_t flags;
|
||||
uint32_t core_mask;
|
||||
uint32_t dram_size; /**< DRAM size in megabyes */
|
||||
uint32_t phy_mem_desc_addr; /**< physical address of free memory descriptor block*/
|
||||
uint32_t debugger_flags_base_addr; /**< used to pass flags from app to debugger */
|
||||
uint32_t eclock_hz; /**< CPU clock speed, in hz */
|
||||
uint32_t dclock_hz; /**< DRAM clock speed, in hz */
|
||||
uint32_t spi_clock_hz; /**< SPI4 clock in hz */
|
||||
uint16_t board_type;
|
||||
uint8_t board_rev_major;
|
||||
uint8_t board_rev_minor;
|
||||
uint16_t chip_type;
|
||||
uint8_t chip_rev_major;
|
||||
uint8_t chip_rev_minor;
|
||||
char board_serial_number[OCTOEN_SERIAL_LEN];
|
||||
uint8_t mac_addr_base[6];
|
||||
uint8_t mac_addr_count;
|
||||
uint64_t cvmx_desc_vaddr;
|
||||
|
||||
} octeon_boot_descriptor_t;
|
||||
|
||||
|
||||
typedef struct {
|
||||
uint32_t major_version;
|
||||
uint32_t minor_version;
|
||||
|
||||
uint64_t stack_top;
|
||||
uint64_t heap_base;
|
||||
uint64_t heap_end;
|
||||
uint64_t desc_vaddr;
|
||||
|
||||
uint32_t exception_base_addr;
|
||||
uint32_t stack_size;
|
||||
uint32_t flags;
|
||||
uint32_t core_mask;
|
||||
uint32_t dram_size; /**< DRAM size in megabyes */
|
||||
uint32_t phy_mem_desc_addr; /**< physical address of free memory descriptor block*/
|
||||
uint32_t debugger_flags_base_addr; /**< used to pass flags from app to debugger */
|
||||
uint32_t eclock_hz; /**< CPU clock speed, in hz */
|
||||
uint32_t dclock_hz; /**< DRAM clock speed, in hz */
|
||||
uint32_t spi_clock_hz; /**< SPI4 clock in hz */
|
||||
uint16_t board_type;
|
||||
uint8_t board_rev_major;
|
||||
uint8_t board_rev_minor;
|
||||
uint16_t chip_type;
|
||||
uint8_t chip_rev_major;
|
||||
uint8_t chip_rev_minor;
|
||||
char board_serial_number[OCTOEN_SERIAL_LEN];
|
||||
uint8_t mac_addr_base[6];
|
||||
uint8_t mac_addr_count;
|
||||
|
||||
} cvmx_bootinfo_t;
|
||||
|
||||
uint32_t octeon_cpu_clock;
|
||||
uint64_t octeon_dram;
|
||||
uint32_t octeon_bd_ver = 0, octeon_cvmx_bd_ver = 0, octeon_board_rev_major, octeon_board_rev_minor, octeon_board_type;
|
||||
uint8_t octeon_mac_addr[6] = { 0 };
|
||||
int octeon_core_mask, octeon_mac_addr_count;
|
||||
int octeon_chip_rev_major = 0, octeon_chip_rev_minor = 0, octeon_chip_type = 0;
|
||||
|
||||
#if defined(__mips_n64)
|
||||
extern uint64_t app_descriptor_addr;
|
||||
#else
|
||||
extern uint32_t app_descriptor_addr;
|
||||
#endif
|
||||
static octeon_boot_descriptor_t *app_desc_ptr;
|
||||
static cvmx_bootinfo_t *cvmx_desc_ptr;
|
||||
|
||||
#define OCTEON_BOARD_TYPE_NONE 0
|
||||
#define OCTEON_BOARD_TYPE_SIM 1
|
||||
|
||||
#define OCTEON_CLOCK_MIN (100 * 1000 * 1000)
|
||||
#define OCTEON_CLOCK_MAX (800 * 1000 * 1000)
|
||||
#define OCTEON_DRAM_DEFAULT (256 * 1024 * 1024)
|
||||
#define OCTEON_DRAM_MIN 30
|
||||
#define OCTEON_DRAM_MAX 3000
|
||||
|
||||
|
||||
int octeon_board_real (void)
|
||||
{
|
||||
if ((octeon_board_type == OCTEON_BOARD_TYPE_NONE) ||
|
||||
(octeon_board_type == OCTEON_BOARD_TYPE_SIM) ||
|
||||
!octeon_board_rev_major) {
|
||||
return 0;
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
static void octeon_process_app_desc_ver_unknown (void)
|
||||
{
|
||||
printf(" Unknown Boot-Descriptor: Using Defaults\n");
|
||||
|
||||
octeon_cpu_clock = OCTEON_CLOCK_DEFAULT;
|
||||
octeon_dram = OCTEON_DRAM_DEFAULT;
|
||||
octeon_board_rev_major = octeon_board_rev_minor = octeon_board_type = 0;
|
||||
|
||||
octeon_core_mask = 1;
|
||||
octeon_cpu_clock = OCTEON_CLOCK_DEFAULT;
|
||||
octeon_chip_type = octeon_chip_rev_major = octeon_chip_rev_minor = 0;
|
||||
|
||||
octeon_mac_addr[0] = 0x00; octeon_mac_addr[1] = 0x0f;
|
||||
octeon_mac_addr[2] = 0xb7; octeon_mac_addr[3] = 0x10;
|
||||
octeon_mac_addr[4] = 0x09; octeon_mac_addr[5] = 0x06;
|
||||
octeon_mac_addr_count = 1;
|
||||
}
|
||||
|
||||
static int octeon_process_app_desc_ver_6 (void)
|
||||
{
|
||||
cvmx_desc_ptr = (cvmx_bootinfo_t *) ((long) app_desc_ptr->cvmx_desc_vaddr);
|
||||
|
||||
if ((cvmx_desc_ptr == NULL) || (cvmx_desc_ptr == (cvmx_bootinfo_t *)0xffffffff)) {
|
||||
printf ("Bad cvmx_desc_ptr 0x%X\n", cvmx_desc_ptr);
|
||||
return 1;
|
||||
}
|
||||
|
||||
cvmx_desc_ptr = (cvmx_bootinfo_t *) (((long) cvmx_desc_ptr) | MIPS_KSEG0_START);
|
||||
octeon_cvmx_bd_ver = (cvmx_desc_ptr->major_version * 100) +
|
||||
cvmx_desc_ptr->minor_version;
|
||||
|
||||
if (cvmx_desc_ptr->major_version != 1) {
|
||||
printf("Incompatible CVMX descriptor from bootloader: %d.%d 0x%X\n",
|
||||
(int) cvmx_desc_ptr->major_version,
|
||||
(int) cvmx_desc_ptr->minor_version, cvmx_desc_ptr);
|
||||
while (1); /* Never return */
|
||||
return 1; /* Satisfy the compiler */
|
||||
}
|
||||
|
||||
octeon_core_mask = cvmx_desc_ptr->core_mask;
|
||||
octeon_cpu_clock = cvmx_desc_ptr->eclock_hz;
|
||||
octeon_board_type = cvmx_desc_ptr->board_type;
|
||||
octeon_board_rev_major = cvmx_desc_ptr->board_rev_major;
|
||||
octeon_board_rev_minor = cvmx_desc_ptr->board_rev_minor;
|
||||
octeon_chip_type = cvmx_desc_ptr->chip_type;
|
||||
octeon_chip_rev_major = cvmx_desc_ptr->chip_rev_major;
|
||||
octeon_chip_rev_minor = cvmx_desc_ptr->chip_rev_minor;
|
||||
octeon_mac_addr[0] = cvmx_desc_ptr->mac_addr_base[0];
|
||||
octeon_mac_addr[1] = cvmx_desc_ptr->mac_addr_base[1];
|
||||
octeon_mac_addr[2] = cvmx_desc_ptr->mac_addr_base[2];
|
||||
octeon_mac_addr[3] = cvmx_desc_ptr->mac_addr_base[3];
|
||||
octeon_mac_addr[4] = cvmx_desc_ptr->mac_addr_base[4];
|
||||
octeon_mac_addr[5] = cvmx_desc_ptr->mac_addr_base[5];
|
||||
octeon_mac_addr_count = cvmx_desc_ptr->mac_addr_count;
|
||||
|
||||
if (app_desc_ptr->dram_size > 16*1024*1024) {
|
||||
octeon_dram = (uint64_t)app_desc_ptr->dram_size;
|
||||
} else {
|
||||
octeon_dram = (uint64_t)app_desc_ptr->dram_size * 1024 * 1024;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int octeon_process_app_desc_ver_3_4_5 (void)
|
||||
{
|
||||
|
||||
octeon_cvmx_bd_ver = octeon_bd_ver;
|
||||
octeon_core_mask = app_desc_ptr->core_mask;
|
||||
|
||||
if (app_desc_ptr->desc_version > 3) {
|
||||
octeon_cpu_clock = app_desc_ptr->eclock_hz;
|
||||
} else {
|
||||
octeon_cpu_clock = OCTEON_CLOCK_DEFAULT;
|
||||
}
|
||||
|
||||
if (app_desc_ptr->dram_size > 16*1024*1024) {
|
||||
octeon_dram = (uint64_t)app_desc_ptr->dram_size;
|
||||
} else {
|
||||
octeon_dram = (uint64_t)app_desc_ptr->dram_size * 1024 * 1024;
|
||||
}
|
||||
|
||||
if (app_desc_ptr->desc_version > 4) {
|
||||
octeon_board_type = app_desc_ptr->board_type;
|
||||
octeon_board_rev_major = app_desc_ptr->board_rev_major;
|
||||
octeon_board_rev_minor = app_desc_ptr->board_rev_minor;
|
||||
octeon_chip_type = app_desc_ptr->chip_type;
|
||||
octeon_chip_rev_major = app_desc_ptr->chip_rev_major;
|
||||
octeon_chip_rev_minor = app_desc_ptr->chip_rev_minor;
|
||||
|
||||
octeon_mac_addr[0] = app_desc_ptr->mac_addr_base[0];
|
||||
octeon_mac_addr[1] = app_desc_ptr->mac_addr_base[1];
|
||||
octeon_mac_addr[2] = app_desc_ptr->mac_addr_base[2];
|
||||
octeon_mac_addr[3] = app_desc_ptr->mac_addr_base[3];
|
||||
octeon_mac_addr[4] = app_desc_ptr->mac_addr_base[4];
|
||||
octeon_mac_addr[5] = app_desc_ptr->mac_addr_base[5];
|
||||
octeon_mac_addr_count = app_desc_ptr->mac_addr_count;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
void mips_boot_params_init(void);
|
||||
|
||||
void mips_boot_params_init (void)
|
||||
{
|
||||
int descriptor_not_parsed = 1;
|
||||
|
||||
if ((app_descriptor_addr == 0) || (app_descriptor_addr >= MAX_APP_DESC_ADDR)) {
|
||||
|
||||
} else {
|
||||
|
||||
app_desc_ptr = (octeon_boot_descriptor_t *) app_descriptor_addr;
|
||||
octeon_bd_ver = app_desc_ptr->desc_version;
|
||||
|
||||
if ((octeon_bd_ver >= 3) && (octeon_bd_ver <= 5)) {
|
||||
descriptor_not_parsed = octeon_process_app_desc_ver_3_4_5();
|
||||
|
||||
} else if (app_desc_ptr->desc_version == 6) {
|
||||
descriptor_not_parsed = octeon_process_app_desc_ver_6();
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
if (descriptor_not_parsed) {
|
||||
octeon_process_app_desc_ver_unknown();
|
||||
}
|
||||
|
||||
printf("Boot Descriptor Ver: %u -> %u/%u",
|
||||
octeon_bd_ver, octeon_cvmx_bd_ver/100, octeon_cvmx_bd_ver%100);
|
||||
printf(" CPU clock: %uMHz\n", octeon_cpu_clock/1000000);
|
||||
printf(" Dram: %u MB", (uint32_t)(octeon_dram >> 20));
|
||||
printf(" Board Type: %u Revision: %u/%u\n",
|
||||
octeon_board_type, octeon_board_rev_major, octeon_board_rev_minor);
|
||||
printf(" Octeon Chip: %u Rev %u/%u",
|
||||
octeon_chip_type, octeon_chip_rev_major, octeon_chip_rev_minor);
|
||||
|
||||
printf(" Mac Address %02X.%02X.%02X.%02X.%02X.%02X\n",
|
||||
octeon_mac_addr[0], octeon_mac_addr[1], octeon_mac_addr[2],
|
||||
octeon_mac_addr[3], octeon_mac_addr[4], octeon_mac_addr[5]);
|
||||
}
|
||||
246
sys/mips/mips4k/octeon32/octeonreg.h
Normal file
246
sys/mips/mips4k/octeon32/octeonreg.h
Normal file
|
|
@ -0,0 +1,246 @@
|
|||
/* $NetBSD: octeonreg.h,v 1.1 2002/03/07 14:44:04 simonb Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright 2002 Wasabi Systems, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Written by Simon Burge for Wasabi Systems, Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed for the NetBSD Project by
|
||||
* Wasabi Systems, Inc.
|
||||
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
|
||||
* or promote products derived from this software without specific prior
|
||||
* written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/*
|
||||
Memory Map
|
||||
|
||||
0000.0000 * 128MB Typically SDRAM (on Core Board)
|
||||
0800.0000 * 256MB Typically PCI
|
||||
1800.0000 * 62MB Typically PCI
|
||||
1be0.0000 * 2MB Typically System controller's internal registers
|
||||
1c00.0000 * 32MB Typically not used
|
||||
1e00.0000 4MB Monitor Flash
|
||||
1e40.0000 12MB reserved
|
||||
1f00.0000 12MB Switches
|
||||
LEDs
|
||||
ASCII display
|
||||
Soft reset
|
||||
FPGA revision number
|
||||
CBUS UART (tty2)
|
||||
General Purpose I/O
|
||||
I2C controller
|
||||
1f10.0000 * 11MB Typically System Controller specific
|
||||
1fc0.0000 4MB Maps to Monitor Flash
|
||||
1fd0.0000 * 3MB Typically System Controller specific
|
||||
|
||||
* depends on implementation of the Core Board and of software
|
||||
*/
|
||||
|
||||
/*
|
||||
CPU interrupts
|
||||
|
||||
NMI South Bridge or NMI button
|
||||
0 South Bridge INTR
|
||||
1 South Bridge SMI
|
||||
2 CBUS UART (tty2)
|
||||
3 COREHI (Core Card)
|
||||
4 CORELO (Core Card)
|
||||
5 Not used, driven inactive (typically CPU internal timer interrupt
|
||||
|
||||
IRQ mapping (as used by YAMON)
|
||||
|
||||
0 Timer South Bridge
|
||||
1 Keyboard SuperIO
|
||||
2 Reserved by South Bridge (for cascading)
|
||||
3 UART (tty1) SuperIO
|
||||
4 UART (tty0) SuperIO
|
||||
5 Not used
|
||||
6 Floppy Disk SuperIO
|
||||
7 Parallel Port SuperIO
|
||||
8 Real Time Clock South Bridge
|
||||
9 I2C bus South Bridge
|
||||
10 PCI A,B,eth PCI slot 1..4, Ethernet
|
||||
11 PCI C,audio PCI slot 1..4, Audio, USB (South Bridge)
|
||||
PCI D,USB
|
||||
12 Mouse SuperIO
|
||||
13 Reserved by South Bridge
|
||||
14 Primary IDE Primary IDE slot
|
||||
15 Secondary IDE Secondary IDE slot/Compact flash connector
|
||||
*/
|
||||
|
||||
#define OCTEON_SYSTEMRAM_BASE 0x00000000 /* System RAM: */
|
||||
#define OCTEON_SYSTEMRAM_SIZE 0x08000000 /* 128 MByte */
|
||||
|
||||
#define OCTEON_PCIMEM1_BASE 0x08000000 /* PCI 1 memory: */
|
||||
#define OCTEON_PCIMEM1_SIZE 0x08000000 /* 128 MByte */
|
||||
|
||||
#define OCTEON_PCIMEM2_BASE 0x10000000 /* PCI 2 memory: */
|
||||
#define OCTEON_PCIMEM2_SIZE 0x08000000 /* 128 MByte */
|
||||
|
||||
#define OCTEON_PCIMEM3_BASE 0x18000000 /* PCI 3 memory */
|
||||
#define OCTEON_PCIMEM3_SIZE 0x03e00000 /* 62 MByte */
|
||||
|
||||
#define OCTEON_CORECTRL_BASE 0x1be00000 /* Core control: */
|
||||
#define OCTEON_CORECTRL_SIZE 0x00200000 /* 2 MByte */
|
||||
|
||||
#define OCTEON_RESERVED_BASE1 0x1c000000 /* Reserved: */
|
||||
#define OCTEON_RESERVED_SIZE1 0x02000000 /* 32 MByte */
|
||||
|
||||
#define OCTEON_MONITORFLASH_BASE 0x1e000000 /* Monitor Flash: */
|
||||
#define OCTEON_MONITORFLASH_SIZE 0x003e0000 /* 4 MByte */
|
||||
#define OCTEON_MONITORFLASH_SECTORSIZE 0x00010000 /* Sect. = 64 KB */
|
||||
|
||||
#define OCTEON_FILEFLASH_BASE 0x1e3e0000 /* File Flash (for monitor): */
|
||||
#define OCTEON_FILEFLASH_SIZE 0x00020000 /* 128 KByte */
|
||||
|
||||
#define OCTEON_FILEFLASH_SECTORSIZE 0x00010000 /* Sect. = 64 KB */
|
||||
|
||||
#define OCTEON_RESERVED_BASE2 0x1e400000 /* Reserved: */
|
||||
#define OCTEON_RESERVED_SIZE2 0x00c00000 /* 12 MByte */
|
||||
|
||||
#define OCTEON_FPGA_BASE 0x1f000000 /* FPGA: */
|
||||
#define OCTEON_FPGA_SIZE 0x00c00000 /* 12 MByte */
|
||||
|
||||
#define OCTEON_NMISTATUS (OCTEON_FPGA_BASE + 0x24)
|
||||
#define OCTEON_NMI_SB 0x2 /* Pending NMI from the South Bridge */
|
||||
#define OCTEON_NMI_ONNMI 0x1 /* Pending NMI from the ON/NMI push button */
|
||||
|
||||
#define OCTEON_NMIACK (OCTEON_FPGA_BASE + 0x104)
|
||||
#define OCTEON_NMIACK_ONNMI 0x1 /* Write 1 to acknowledge ON/NMI */
|
||||
|
||||
#define OCTEON_SWITCH (OCTEON_FPGA_BASE + 0x200)
|
||||
#define OCTEON_SWITCH_MASK 0xff /* settings of DIP switch S2 */
|
||||
|
||||
#define OCTEON_STATUS (OCTEON_FPGA_BASE + 0x208)
|
||||
#define OCTEON_ST_MFWR 0x10 /* Monitor Flash is write protected (JP1) */
|
||||
#define OCTEON_S54 0x08 /* switch S5-4 - set YAMON factory default mode */
|
||||
#define OCTEON_S53 0x04 /* switch S5-3 */
|
||||
#define OCTEON_BIGEND 0x02 /* switch S5-2 - big endian mode */
|
||||
|
||||
#define OCTEON_JMPRS (OCTEON_FPGA_BASE + 0x210)
|
||||
#define OCTEON_JMPRS_PCICLK 0x1c /* PCI clock frequency */
|
||||
#define OCTEON_JMPRS_EELOCK 0x02 /* I2C EEPROM is write protected */
|
||||
|
||||
#define OCTEON_LEDBAR (OCTEON_FPGA_BASE + 0x408)
|
||||
#define OCTEON_ASCIIWORD (OCTEON_FPGA_BASE + 0x410)
|
||||
#define OCTEON_ASCII_BASE (OCTEON_FPGA_BASE + 0x418)
|
||||
#define OCTEON_ASCIIPOS0 0x00
|
||||
#define OCTEON_ASCIIPOS1 0x08
|
||||
#define OCTEON_ASCIIPOS2 0x10
|
||||
#define OCTEON_ASCIIPOS3 0x18
|
||||
#define OCTEON_ASCIIPOS4 0x20
|
||||
#define OCTEON_ASCIIPOS5 0x28
|
||||
#define OCTEON_ASCIIPOS6 0x30
|
||||
#define OCTEON_ASCIIPOS7 0x38
|
||||
|
||||
#define OCTEON_SOFTRES (OCTEON_FPGA_BASE + 0x500)
|
||||
#define OCTEON_GORESET 0x42 /* write this to OCTEON_SOFTRES for board reset */
|
||||
|
||||
/*
|
||||
* BRKRES is the number of milliseconds before a "break" on tty will
|
||||
* trigger a reset. A value of 0 will disable the reset.
|
||||
*/
|
||||
#define OCTEON_BRKRES (OCTEON_FPGA_BASE + 0x508)
|
||||
#define OCTEON_BRKRES_MASK 0xff
|
||||
|
||||
#define OCTEON_CBUSUART 0x8001180000000800ull
|
||||
/* 16C550C UART, 8 bit registers on 8 byte boundaries */
|
||||
/* RXTX 0x00 */
|
||||
/* INTEN 0x08 */
|
||||
/* IIFIFO 0x10 */
|
||||
/* LCTRL 0x18 */
|
||||
/* MCTRL 0x20 */
|
||||
/* LSTAT 0x28 */
|
||||
/* MSTAT 0x30 */
|
||||
/* SCRATCH 0x38 */
|
||||
#define OCTEON_CBUSUART_INTR 2
|
||||
|
||||
#define OCTEON_GPIO_BASE (OCTEON_FPGA_BASE + 0xa00)
|
||||
#define OCTEON_GPOUT 0x0
|
||||
#define OCTEON_GPINP 0x8
|
||||
|
||||
#define OCTEON_BOOTROM_BASE 0x1fc00000 /* Boot ROM: */
|
||||
#define OCTEON_BOOTROM_SIZE 0x00400000 /* 4 MByte */
|
||||
|
||||
#define OCTEON_REVISION 0x1fc00010
|
||||
#define OCTEON_REV_FPGRV 0xff0000 /* CBUS FPGA revision */
|
||||
#define OCTEON_REV_CORID 0x00fc00 /* Core Board ID */
|
||||
#define OCTEON_REV_CORRV 0x000300 /* Core Board Revision */
|
||||
#define OCTEON_REV_PROID 0x0000f0 /* Product ID */
|
||||
#define OCTEON_REV_PRORV 0x00000f /* Product Revision */
|
||||
|
||||
/* PCI definitions */
|
||||
|
||||
#define OCTEON_UART0ADR 0x8001180000000800ull
|
||||
#define OCTEON_UART1ADR 0x8001180000000C00ull
|
||||
|
||||
#define OCTEON_MIO_BOOT_BIST_STAT 0x80011800000000F8ull
|
||||
|
||||
|
||||
|
||||
/**************************
|
||||
* To Delete
|
||||
*/
|
||||
#define OCTEON_SOUTHBRIDGE_INTR 0
|
||||
|
||||
#define OCTEON_PCI0_IO_BASE OCTEON_PCIMEM3_BASE
|
||||
#define OCTEON_PCI0_ADDR( addr ) (OCTEON_PCI0_IO_BASE + (addr))
|
||||
|
||||
#define OCTEON_RTCADR 0x70 // OCTEON_PCI_IO_ADDR8(0x70)
|
||||
#define OCTEON_RTCDAT 0x71 // OCTEON_PCI_IO_ADDR8(0x71)
|
||||
|
||||
#define OCTEON_SMSC_COM1_ADR 0x3f8
|
||||
#define OCTEON_SMSC_COM2_ADR 0x2f8
|
||||
#define OCTEON_UARTT0ADR OCTEON_PCI0_ADDR(OCTEON_SMSC_COM1_ADR)
|
||||
#define OCTEON_UARTT1ADR OCTEON_SMSC_COM2_ADR // OCTEON_PCI0_ADDR(OCTEON_SMSC_COM2_ADR)
|
||||
|
||||
#define OCTEON_SMSC_1284_ADR 0x378
|
||||
#define OCTEON_1284ADR OCTEON_SMSC_1284_ADR // OCTEON_PCI0_ADDR(OCTEON_SMSC_1284_ADR)
|
||||
|
||||
#define OCTEON_SMSC_FDD_ADR 0x3f0
|
||||
#define OCTEON_FDDADR OCTEON_SMSC_FDD_ADR // OCTEON_PCI0_ADDR(OCTEON_SMSC_FDD_ADR)
|
||||
|
||||
#define OCTEON_SMSC_KYBD_ADR 0x60 /* Fixed 0x60, 0x64 */
|
||||
#define OCTEON_KYBDADR OCTEON_SMSC_KYBD_ADR // OCTEON_PCI0_ADDR(OCTEON_SMSC_KYBD_ADR)
|
||||
#define OCTEON_SMSC_MOUSE_ADR OCTEON_SMSC_KYBD_ADR
|
||||
#define OCTEON_MOUSEADR OCTEON_KYBDADR
|
||||
|
||||
|
||||
#define OCTEON_DMA_PCI_PCIBASE 0x00000000UL
|
||||
#define OCTEON_DMA_PCI_PHYSBASE 0x00000000UL
|
||||
#define OCTEON_DMA_PCI_SIZE (256 * 1024 * 1024)
|
||||
|
||||
#define OCTEON_DMA_ISA_PCIBASE 0x00800000UL
|
||||
#define OCTEON_DMA_ISA_PHYSBASE 0x00000000UL
|
||||
#define OCTEON_DMA_ISA_SIZE (8 * 1024 * 1024)
|
||||
|
||||
#ifndef _LOCORE
|
||||
void led_bar(uint8_t);
|
||||
void led_display_word(uint32_t);
|
||||
void led_display_str(const char *);
|
||||
void led_display_char(int, uint8_t);
|
||||
#endif
|
||||
21
sys/mips/mips4k/octeon32/std.octeon32
Normal file
21
sys/mips/mips4k/octeon32/std.octeon32
Normal file
|
|
@ -0,0 +1,21 @@
|
|||
# /*
|
||||
# * This product includes software developed by the University of
|
||||
# * California, Berkeley and its contributors."
|
||||
# */
|
||||
# $FreeBSD$
|
||||
#
|
||||
include "../mips4k/std.mips4k"
|
||||
files "../mips4k/octeon32/files.octeon32"
|
||||
|
||||
#
|
||||
#
|
||||
#
|
||||
cpu CPU_MIPS4KC
|
||||
#device pci
|
||||
#device ata
|
||||
#device atadisk
|
||||
|
||||
#device clock
|
||||
#device obio
|
||||
#device uart
|
||||
|
||||
119
sys/mips/mips4k/octeon32/uart_bus_octeonusart.c
Normal file
119
sys/mips/mips4k/octeon32/uart_bus_octeonusart.c
Normal file
|
|
@ -0,0 +1,119 @@
|
|||
/*-
|
||||
* Copyright (c) 2006 Wojciech A. Koszek <wkoszek@FreeBSD.org>
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* $Id$
|
||||
*/
|
||||
/*
|
||||
* Skeleton of this file was based on respective code for ARM
|
||||
* code written by Olivier Houchard.
|
||||
*/
|
||||
|
||||
/*
|
||||
* XXXMIPS: This file is hacked from arm/... . XXXMIPS here means this file is
|
||||
* experimental and was written for MIPS32 port.
|
||||
*/
|
||||
#include "opt_uart.h"
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD$");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/bus.h>
|
||||
#include <sys/conf.h>
|
||||
#include <sys/kernel.h>
|
||||
#include <sys/module.h>
|
||||
#include <machine/bus.h>
|
||||
#include <sys/rman.h>
|
||||
#include <machine/resource.h>
|
||||
|
||||
#include <dev/pci/pcivar.h>
|
||||
|
||||
#include <dev/uart/uart.h>
|
||||
#include <dev/uart/uart_bus.h>
|
||||
#include <dev/uart/uart_cpu.h>
|
||||
|
||||
/*
|
||||
* XXXMIPS:
|
||||
*/
|
||||
#include <mips/mips4k/octeon32/octeonreg.h>
|
||||
|
||||
#include "uart_if.h"
|
||||
|
||||
static int uart_octeon_probe(device_t dev);
|
||||
static void octeon_uart_identify(driver_t *drv, device_t parent);
|
||||
|
||||
extern struct uart_class octeon_uart_class;
|
||||
|
||||
static device_method_t uart_octeon_methods[] = {
|
||||
/* Device interface */
|
||||
DEVMETHOD(device_probe, uart_octeon_probe),
|
||||
DEVMETHOD(device_attach, uart_bus_attach),
|
||||
DEVMETHOD(device_detach, uart_bus_detach),
|
||||
DEVMETHOD(device_identify, octeon_uart_identify),
|
||||
{ 0, 0 }
|
||||
};
|
||||
|
||||
static driver_t uart_octeon_driver = {
|
||||
uart_driver_name,
|
||||
uart_octeon_methods,
|
||||
sizeof(struct uart_softc),
|
||||
};
|
||||
|
||||
extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs;
|
||||
static int
|
||||
uart_octeon_probe (device_t dev)
|
||||
{
|
||||
struct uart_softc *sc;
|
||||
int unit;
|
||||
|
||||
/*
|
||||
* Note that both tty0 & tty1 are viable consoles. We add child devices
|
||||
* such that ttyu0 ends up front of queue.
|
||||
*/
|
||||
unit = device_get_unit(dev);
|
||||
sc = device_get_softc(dev);
|
||||
sc->sc_sysdev = NULL;
|
||||
sc->sc_sysdev = SLIST_FIRST(&uart_sysdevs);
|
||||
bcopy(&sc->sc_sysdev->bas, &sc->sc_bas, sizeof(sc->sc_bas));
|
||||
if (!unit) {
|
||||
sc->sc_sysdev->bas.bst = 0;
|
||||
sc->sc_sysdev->bas.bsh = OCTEON_UART0ADR;
|
||||
}
|
||||
sc->sc_class = &uart_oct16550_class;
|
||||
sc->sc_bas.bst = 0;
|
||||
sc->sc_bas.bsh = unit ? OCTEON_UART1ADR : OCTEON_UART0ADR;
|
||||
sc->sc_bas.regshft = 0x3;
|
||||
return (uart_bus_probe(dev, sc->sc_bas.regshft, 0, 0, unit));
|
||||
}
|
||||
|
||||
static void
|
||||
octeon_uart_identify (driver_t *drv, device_t parent)
|
||||
{
|
||||
BUS_ADD_CHILD(parent, 0, "uart", 0);
|
||||
}
|
||||
|
||||
|
||||
|
||||
DRIVER_MODULE(uart, obio, uart_octeon_driver, uart_devclass, 0, 0);
|
||||
|
||||
83
sys/mips/mips4k/octeon32/uart_cpu_octeonusart.c
Normal file
83
sys/mips/mips4k/octeon32/uart_cpu_octeonusart.c
Normal file
|
|
@ -0,0 +1,83 @@
|
|||
/*-
|
||||
* Copyright (c) 2006 Wojciech A. Koszek <wkoszek@FreeBSD.org>
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
/*
|
||||
* Skeleton of this file was based on respective code for ARM
|
||||
* code written by Olivier Houchard.
|
||||
*/
|
||||
/*
|
||||
* XXXMIPS: This file is hacked from arm/... . XXXMIPS here means this file is
|
||||
* experimental and was written for MIPS32 port.
|
||||
*/
|
||||
#include "opt_uart.h"
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD$");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/bus.h>
|
||||
#include <sys/cons.h>
|
||||
|
||||
#include <machine/bus.h>
|
||||
|
||||
#include <dev/uart/uart.h>
|
||||
#include <dev/uart/uart_cpu.h>
|
||||
|
||||
#include <mips/mips4k/octeon32/octeonreg.h>
|
||||
|
||||
bus_space_tag_t uart_bus_space_io;
|
||||
bus_space_tag_t uart_bus_space_mem;
|
||||
|
||||
extern struct uart_ops octeon_usart_ops;
|
||||
extern struct bus_space octeon_bs_tag;
|
||||
|
||||
int
|
||||
uart_cpu_eqres(struct uart_bas *b1, struct uart_bas *b2)
|
||||
{
|
||||
return ((b1->bsh == b2->bsh && b1->bst == b2->bst) ? 1 : 0);
|
||||
return (0);
|
||||
}
|
||||
|
||||
int
|
||||
uart_cpu_getdev(int devtype, struct uart_devinfo *di)
|
||||
{
|
||||
di->ops = uart_getops(&uart_oct16550_class);
|
||||
di->bas.chan = 0;
|
||||
di->bas.bst = 0;
|
||||
di->bas.regshft = 3; /* Each UART reg is 8 byte addresss apart. 1 << 3 */
|
||||
di->bas.rclk = 0;
|
||||
di->baudrate = 115200;
|
||||
di->databits = 8;
|
||||
di->stopbits = 1;
|
||||
di->parity = UART_PARITY_NONE;
|
||||
|
||||
uart_bus_space_io = MIPS_PHYS_TO_KSEG1(OCTEON_UART0ADR);
|
||||
uart_bus_space_mem = MIPS_PHYS_TO_KSEG1(OCTEON_UART0ADR);
|
||||
di->bas.bsh = OCTEON_UART0ADR;
|
||||
return (0);
|
||||
}
|
||||
5
sys/mips/mips4k/std.mips4k
Normal file
5
sys/mips/mips4k/std.mips4k
Normal file
|
|
@ -0,0 +1,5 @@
|
|||
# /*
|
||||
# * This product includes software developed by the University of
|
||||
# * California, Berkeley and its contributors."
|
||||
# */
|
||||
# $FreeBSD$
|
||||
Loading…
Reference in a new issue