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On Dell boxes such as the PE2650 we need to disable 3 led mode for the

Browse source 
link LED to work.

Reviewed by:	wpaul
Obtained from:	Linux driver
This commit is contained in:
Doug Ambrisko 2003-08-20 04:06:00 +00:00
parent e8ef0c2923
commit 6d2a9bd669
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=119157
3 changed files with 16 additions and 0 deletions
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2
sys/dev/bge/if_bge.c
View file

@ -1736,6 +1736,8 @@ bge_probe(dev)
"%s, ASIC rev. %#04x", t->bge_name,
pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 16);
device_set_desc_copy(dev, descbuf);
if (pci_get_subvendor(dev) == DELL_VENDORID)
sc->bge_no_3_led = 1;
free(descbuf, M_TEMP);
return(0);
}

7
sys/dev/bge/if_bgereg.h
View file

@ -1856,6 +1856,12 @@ struct bge_status_block {
#define ALTIMA_DEVICE_AC1000 0x03e8
#define ALTIMA_DEVICE_AC9100 0x03ea
/*
* Dell PCI vendor ID
*/
#define DELL_VENDORID 0x1028
/*
* Offset of MAC address inside EEPROM.
*/
@ -2267,6 +2273,7 @@ struct bge_softc {
u_int32_t bge_chipid;
u_int8_t bge_asicrev;
u_int8_t bge_chiprev;
u_int8_t bge_no_3_led;
struct bge_ring_data bge_ldata; /* rings */
struct bge_chain_data bge_cdata; /* mbufs */
u_int16_t bge_tx_saved_considx;

7
sys/dev/mii/brgphy.c
View file

@ -620,4 +620,11 @@ brgphy_reset(struct mii_softc *sc)
PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007);
val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) || (1 << 4));
/* Enable Link LED on Dell boxes */
if (bge_sc->bge_no_3_led) {
PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL)
& ~BRGPHY_PHY_EXTCTL_3_LED);
}
}