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https://github.com/freebsd/freebsd-src
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Fix previous fix: The enable bit is bit 31 (0x8000000) and not bit 15.
This commit is contained in:
parent
e0c57a9615
commit
64039d403f
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=26173
6 changed files with 12 additions and 12 deletions
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@ -23,7 +23,7 @@
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $Id: pcibus.c,v 1.36 1997/05/26 15:08:42 se Exp $
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* $Id: pcibus.c,v 1.37 1997/05/26 21:11:05 se Exp $
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*
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*/
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@ -59,7 +59,7 @@ pci_cfgenable(unsigned bus, unsigned slot, unsigned func, int reg, int bytes)
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&& (reg & (bytes -1)) == 0) {
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switch (cfgmech) {
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case 1:
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outl(CONF1_ADDR_PORT, 0x8000 |
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outl(CONF1_ADDR_PORT, (1 << 31) |
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(bus << 16) | (slot << 11) | (func << 8) | reg);
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dataport = CONF1_DATA_PORT;
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break;
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@ -23,7 +23,7 @@
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $Id: pcibus.c,v 1.36 1997/05/26 15:08:42 se Exp $
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* $Id: pcibus.c,v 1.37 1997/05/26 21:11:05 se Exp $
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*
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*/
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@ -59,7 +59,7 @@ pci_cfgenable(unsigned bus, unsigned slot, unsigned func, int reg, int bytes)
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&& (reg & (bytes -1)) == 0) {
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switch (cfgmech) {
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case 1:
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outl(CONF1_ADDR_PORT, 0x8000 |
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outl(CONF1_ADDR_PORT, (1 << 31) |
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(bus << 16) | (slot << 11) | (func << 8) | reg);
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dataport = CONF1_DATA_PORT;
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break;
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@ -23,7 +23,7 @@
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $Id: pcibus.c,v 1.36 1997/05/26 15:08:42 se Exp $
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* $Id: pcibus.c,v 1.37 1997/05/26 21:11:05 se Exp $
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*
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*/
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@ -59,7 +59,7 @@ pci_cfgenable(unsigned bus, unsigned slot, unsigned func, int reg, int bytes)
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&& (reg & (bytes -1)) == 0) {
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switch (cfgmech) {
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case 1:
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outl(CONF1_ADDR_PORT, 0x8000 |
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outl(CONF1_ADDR_PORT, (1 << 31) |
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(bus << 16) | (slot << 11) | (func << 8) | reg);
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dataport = CONF1_DATA_PORT;
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break;
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@ -23,7 +23,7 @@
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $Id: pcibus.c,v 1.36 1997/05/26 15:08:42 se Exp $
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* $Id: pcibus.c,v 1.37 1997/05/26 21:11:05 se Exp $
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*
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*/
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@ -59,7 +59,7 @@ pci_cfgenable(unsigned bus, unsigned slot, unsigned func, int reg, int bytes)
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&& (reg & (bytes -1)) == 0) {
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switch (cfgmech) {
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case 1:
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outl(CONF1_ADDR_PORT, 0x8000 |
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outl(CONF1_ADDR_PORT, (1 << 31) |
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(bus << 16) | (slot << 11) | (func << 8) | reg);
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dataport = CONF1_DATA_PORT;
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break;
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@ -23,7 +23,7 @@
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $Id: pcibus.c,v 1.36 1997/05/26 15:08:42 se Exp $
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* $Id: pcibus.c,v 1.37 1997/05/26 21:11:05 se Exp $
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*
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*/
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@ -59,7 +59,7 @@ pci_cfgenable(unsigned bus, unsigned slot, unsigned func, int reg, int bytes)
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&& (reg & (bytes -1)) == 0) {
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switch (cfgmech) {
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case 1:
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outl(CONF1_ADDR_PORT, 0x8000 |
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outl(CONF1_ADDR_PORT, (1 << 31) |
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(bus << 16) | (slot << 11) | (func << 8) | reg);
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dataport = CONF1_DATA_PORT;
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break;
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@ -23,7 +23,7 @@
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $Id: pcibus.c,v 1.36 1997/05/26 15:08:42 se Exp $
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* $Id: pcibus.c,v 1.37 1997/05/26 21:11:05 se Exp $
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*
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*/
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@ -59,7 +59,7 @@ pci_cfgenable(unsigned bus, unsigned slot, unsigned func, int reg, int bytes)
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&& (reg & (bytes -1)) == 0) {
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switch (cfgmech) {
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case 1:
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outl(CONF1_ADDR_PORT, 0x8000 |
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outl(CONF1_ADDR_PORT, (1 << 31) |
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(bus << 16) | (slot << 11) | (func << 8) | reg);
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dataport = CONF1_DATA_PORT;
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break;
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