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arm64: Add support for NanoPI NEO2
Add overlay files and activate devicetree file for NanoPi NEO2 featuring Allwinner H5 ARM64 core. To enable sound, dma and codec drivers are enabled for build. Submitted by: Manuel Stühn (freebsdnewbie@freenet.de) MFC after: 1 month Differential Revision: https://reviews.freebsd.org/D20129
This commit is contained in:
parent
03ddf624e6
commit
5b1309542e
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=347017
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@ -215,11 +215,19 @@ device muge
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device smcphy
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device smsc
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# Sound support
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device sound
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device a10_codec
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# DMA controller
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device a31_dmac
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# GPIO / PINCTRL
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device aw_gpio # Allwinner GPIO controller
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device gpio
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device gpioled
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device fdt_pinctrl
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device gpioregulator
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device mv_gpio # Marvell GPIO controller
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device mvebu_pinctrl # Marvell Pinmux Controller
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device rk_gpio # RockChip GPIO Controller
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@ -27,6 +27,9 @@ cloudabi64_vdso_blob.o optional compat_cloudabi64 \
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# Allwinner common files
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arm/allwinner/a10_ehci.c optional ehci aw_ehci fdt
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arm/allwinner/a10_timer.c optional a10_timer fdt
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arm/allwinner/a10_codec.c optional sound a10_codec
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arm/allwinner/a31_dmac.c optional a31_dmac
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arm/allwinner/sunxi_dma_if.m optional a31_dmac
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arm/allwinner/aw_cir.c optional evdev aw_cir fdt
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arm/allwinner/aw_gpio.c optional gpio aw_gpio fdt
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arm/allwinner/aw_mmc.c optional mmc aw_mmc fdt | mmccam aw_mmc fdt
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32
sys/dts/arm64/overlays/sun50i-h5-nanopi-neo2-opp.dtso
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32
sys/dts/arm64/overlays/sun50i-h5-nanopi-neo2-opp.dtso
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@ -0,0 +1,32 @@
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/dts-v1/;
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/plugin/;
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#include <dt-bindings/gpio/gpio.h>
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/ {
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compatible = "allwinner,sun50i-h5";
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};
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&{/} {
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vdd_cpux: gpio-regulator {
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compatible = "regulator-gpio";
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pinctrl-names = "default";
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regulator-name = "vdd-cpux";
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regulator-type = "voltage";
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regulator-boot-on;
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regulator-always-on;
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regulator-min-microvolt = <1100000>;
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regulator-max-microvolt = <1300000>;
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regulator-ramp-delay = <50>; /* 4ms */
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gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
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gpios-states = <0x1>;
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states = <1100000 0x0
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1300000 0x1>;
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};
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};
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&{/cpus/cpu@0} {
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cpu-supply = <&vdd_cpux>;
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};
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99
sys/dts/arm64/overlays/sun50i-h5-opp.dtso
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99
sys/dts/arm64/overlays/sun50i-h5-opp.dtso
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@ -0,0 +1,99 @@
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/dts-v1/;
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/plugin/;
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#include <dt-bindings/clock/sun8i-h3-ccu.h>
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/ {
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compatible = "allwinner,sun50i-h5";
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};
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&{/} {
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cpu_opp_table: opp_table {
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compatible = "operating-points-v2";
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opp-shared;
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opp@408000000 {
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opp-hz = /bits/ 64 <408000000>;
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opp-microvolt = <1000000 1000000 1300000>;
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clock-latency-ns = <244144>; /* 8 32k periods */
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};
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opp@648000000 {
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opp-hz = /bits/ 64 <648000000>;
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opp-microvolt = <1040000 1040000 1300000>;
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clock-latency-ns = <244144>; /* 8 32k periods */
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};
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opp@816000000 {
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opp-hz = /bits/ 64 <816000000>;
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opp-microvolt = <1080000 1080000 1300000>;
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clock-latency-ns = <244144>; /* 8 32k periods */
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};
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opp@912000000 {
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opp-hz = /bits/ 64 <912000000>;
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opp-microvolt = <1120000 1120000 1300000>;
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clock-latency-ns = <244144>; /* 8 32k periods */
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};
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opp@960000000 {
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opp-hz = /bits/ 64 <960000000>;
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opp-microvolt = <1160000 1160000 1300000>;
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clock-latency-ns = <244144>; /* 8 32k periods */
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};
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opp@1008000000 {
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opp-hz = /bits/ 64 <1008000000>;
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opp-microvolt = <1200000 1200000 1300000>;
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clock-latency-ns = <244144>; /* 8 32k periods */
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};
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opp@1056000000 {
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opp-hz = /bits/ 64 <1056000000>;
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opp-microvolt = <1240000 1240000 1300000>;
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clock-latency-ns = <244144>; /* 8 32k periods */
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};
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opp@1104000000 {
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opp-hz = /bits/ 64 <1104000000>;
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opp-microvolt = <1260000 1260000 1300000>;
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clock-latency-ns = <244144>; /* 8 32k periods */
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};
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opp@1152000000 {
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opp-hz = /bits/ 64 <1152000000>;
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opp-microvolt = <1300000 1300000 1300000>;
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clock-latency-ns = <244144>; /* 8 32k periods */
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};
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};
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reg_cpu_fallback: reg_cpu_fallback {
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compatible = "regulator-fixed";
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regulator-name = "vdd-cpux-dummy";
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regulator-min-microvolt = <1100000>;
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regulator-max-microvolt = <1100000>;
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};
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};
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&{/cpus/cpu@0} {
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clocks = <&ccu CLK_CPUX>;
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clock-names = "cpu";
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clock-latency = <244144>; /* 8 32k periods */
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operating-points-v2 = <&cpu_opp_table>;
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cpu-supply = <®_cpu_fallback>;
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#cooling-cells = <2>;
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};
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&{/cpus/cpu@1} {
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operating-points-v2 = <&cpu_opp_table>;
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};
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&{/cpus/cpu@2} {
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operating-points-v2 = <&cpu_opp_table>;
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};
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&{/cpus/cpu@3} {
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operating-points-v2 = <&cpu_opp_table>;
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};
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17
sys/dts/arm64/overlays/sun50i-h5-sid.dtso
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17
sys/dts/arm64/overlays/sun50i-h5-sid.dtso
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/dts-v1/;
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/plugin/;
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/ {
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compatible = "allwinner,sun50i-h5";
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};
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&{/soc} {
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sid: eeprom@1c14000 {
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compatible = "allwinner,sun50i-h5-sid";
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reg = <0x1c14000 0x400>;
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ths_calib: calib@234 {
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reg = <0x234 0x4>;
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};
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};
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};
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26
sys/dts/arm64/overlays/sun50i-h5-ths.dtso
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26
sys/dts/arm64/overlays/sun50i-h5-ths.dtso
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/dts-v1/;
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/plugin/;
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/sun8i-h3-ccu.h>
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#include <dt-bindings/reset/sun8i-h3-ccu.h>
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/ {
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compatible = "allwinner,sun50i-h5";
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};
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&{/soc} {
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ths: thermal_sensor@1c25000 {
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compatible = "allwinner,sun50i-h5-ths";
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reg = <0x01c25000 0x100>;
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interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
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clock-names = "apb", "ths";
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resets = <&ccu RST_BUS_THS>;
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reset-names = "apb";
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#thermal-sensor-cells = <1>;
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nvmem-cells = <&ths_calib>;
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nvmem-cell-names = "ths-calib";
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};
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};
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@ -44,14 +44,19 @@ DTS= \
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allwinner/sun50i-a64-pine64-plus.dts \
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allwinner/sun50i-a64-pine64.dts \
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allwinner/sun50i-a64-sopine-baseboard.dts \
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allwinner/sun50i-h5-orangepi-pc2.dts
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allwinner/sun50i-h5-orangepi-pc2.dts \
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allwinner/sun50i-h5-nanopi-neo2.dts
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DTSO= sun50i-a64-opp.dtso \
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sun50i-a64-pwm.dtso \
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sun50i-a64-rpwm.dtso \
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sun50i-a64-sid.dtso \
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sun50i-a64-ths.dtso \
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sun50i-a64-timer.dtso
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sun50i-a64-timer.dtso \
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sun50i-h5-opp.dtso \
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sun50i-h5-sid.dtso \
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sun50i-h5-ths.dtso \
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sun50i-h5-nanopi-neo2-opp.dtso
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.endif
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