mirror of
https://github.com/freebsd/freebsd-src
synced 2024-07-22 02:37:15 +00:00
OpenSSL: regenerate asm files for 3.0.12
Fixes: ad991e4c14 ("OpenSSL: update to 3.0.12")
Sponsored by: The FreeBSD Foundation
This commit is contained in:
Ed Maste
parent
876fddc886
commit
575878a533
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@ -106,7 +106,7 @@ aes_v8_set_encrypt_key:
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.Loop192:
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tbl v6.16b,{v4.16b},v2.16b
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ext v5.16b,v0.16b,v3.16b,#12
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#ifdef __ARMEB__
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#ifdef __AARCH64EB__
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st1 {v4.4s},[x2],#16
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sub x2,x2,#8
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#else
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@ -1520,7 +1520,7 @@ aes_v8_ctr32_encrypt_blocks:
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ldr w5,[x3,#240]
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ldr w8, [x4, #12]
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#ifdef __ARMEB__
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#ifdef __AARCH64EB__
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ld1 {v0.16b},[x4]
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#else
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ld1 {v0.4s},[x4]
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@ -1537,7 +1537,7 @@ aes_v8_ctr32_encrypt_blocks:
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add x7,x3,#32
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mov w6,w5
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csel x12,xzr,x12,lo
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#ifndef __ARMEB__
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#ifndef __AARCH64EB__
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rev w8, w8
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#endif
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orr v1.16b,v0.16b,v0.16b
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@ -1,5 +1,5 @@
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/*
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* Copyright 2011-2022 The OpenSSL Project Authors. All Rights Reserved.
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* Copyright 2011-2023 The OpenSSL Project Authors. All Rights Reserved.
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*
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* Licensed under the Apache License 2.0 (the "License"). You may not use
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* this file except in compliance with the License. You can obtain a copy
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@ -21,11 +21,6 @@
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# elif defined(__GNUC__)
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# if defined(__aarch64__)
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# define __ARM_ARCH__ 8
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# if __BYTE_ORDER__==__ORDER_BIG_ENDIAN__
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# define __ARMEB__
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# else
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# define __ARMEL__
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# endif
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/*
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* Why doesn't gcc define __ARM_ARCH__? Instead it defines
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* bunch of below macros. See all_architectures[] table in
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@ -104,7 +104,7 @@ gcm_gmult_v8:
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movi v19.16b,#0xe1
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ld1 {v20.2d,v21.2d},[x1] //load twisted H, ...
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shl v19.2d,v19.2d,#57
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#ifndef __ARMEB__
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#ifndef __AARCH64EB__
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rev64 v17.16b,v17.16b
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#endif
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ext v3.16b,v17.16b,v17.16b,#8
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@ -129,7 +129,7 @@ gcm_gmult_v8:
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eor v18.16b,v18.16b,v2.16b
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eor v0.16b,v0.16b,v18.16b
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#ifndef __ARMEB__
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#ifndef __AARCH64EB__
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rev64 v0.16b,v0.16b
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#endif
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ext v0.16b,v0.16b,v0.16b,#8
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@ -167,14 +167,14 @@ gcm_ghash_v8:
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ext v0.16b,v0.16b,v0.16b,#8 //rotate Xi
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ld1 {v16.2d},[x2],#16 //load [rotated] I[0]
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shl v19.2d,v19.2d,#57 //compose 0xc2.0 constant
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#ifndef __ARMEB__
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#ifndef __AARCH64EB__
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rev64 v16.16b,v16.16b
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rev64 v0.16b,v0.16b
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#endif
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ext v3.16b,v16.16b,v16.16b,#8 //rotate I[0]
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b.lo .Lodd_tail_v8 //x3 was less than 32
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ld1 {v17.2d},[x2],x12 //load [rotated] I[1]
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#ifndef __ARMEB__
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#ifndef __AARCH64EB__
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rev64 v17.16b,v17.16b
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#endif
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ext v7.16b,v17.16b,v17.16b,#8
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@ -206,13 +206,13 @@ gcm_ghash_v8:
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eor v18.16b,v0.16b,v2.16b
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eor v1.16b,v1.16b,v17.16b
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ld1 {v17.2d},[x2],x12 //load [rotated] I[i+3]
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#ifndef __ARMEB__
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#ifndef __AARCH64EB__
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rev64 v16.16b,v16.16b
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#endif
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eor v1.16b,v1.16b,v18.16b
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pmull v18.1q,v0.1d,v19.1d //1st phase of reduction
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#ifndef __ARMEB__
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#ifndef __AARCH64EB__
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rev64 v17.16b,v17.16b
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#endif
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ins v2.d[0],v1.d[1]
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@ -262,7 +262,7 @@ gcm_ghash_v8:
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eor v0.16b,v0.16b,v18.16b
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.Ldone_v8:
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#ifndef __ARMEB__
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#ifndef __AARCH64EB__
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rev64 v0.16b,v0.16b
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#endif
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ext v0.16b,v0.16b,v0.16b,#8
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@ -281,7 +281,7 @@ gcm_ghash_v8_4x:
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shl v19.2d,v19.2d,#57 //compose 0xc2.0 constant
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ld1 {v4.2d,v5.2d,v6.2d,v7.2d},[x2],#64
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#ifndef __ARMEB__
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#ifndef __AARCH64EB__
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rev64 v0.16b,v0.16b
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rev64 v5.16b,v5.16b
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rev64 v6.16b,v6.16b
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@ -325,7 +325,7 @@ gcm_ghash_v8_4x:
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eor v16.16b,v4.16b,v0.16b
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ld1 {v4.2d,v5.2d,v6.2d,v7.2d},[x2],#64
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ext v3.16b,v16.16b,v16.16b,#8
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#ifndef __ARMEB__
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#ifndef __AARCH64EB__
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rev64 v5.16b,v5.16b
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rev64 v6.16b,v6.16b
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rev64 v7.16b,v7.16b
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@ -408,7 +408,7 @@ gcm_ghash_v8_4x:
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eor v1.16b,v1.16b,v17.16b
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ld1 {v4.2d,v5.2d,v6.2d},[x2]
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eor v1.16b,v1.16b,v18.16b
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#ifndef __ARMEB__
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#ifndef __AARCH64EB__
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rev64 v5.16b,v5.16b
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rev64 v6.16b,v6.16b
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rev64 v4.16b,v4.16b
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@ -460,7 +460,7 @@ gcm_ghash_v8_4x:
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eor v1.16b,v1.16b,v17.16b
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ld1 {v4.2d,v5.2d},[x2]
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eor v1.16b,v1.16b,v18.16b
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#ifndef __ARMEB__
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#ifndef __AARCH64EB__
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rev64 v5.16b,v5.16b
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rev64 v4.16b,v4.16b
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#endif
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@ -503,7 +503,7 @@ gcm_ghash_v8_4x:
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eor v1.16b,v1.16b,v17.16b
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ld1 {v4.2d},[x2]
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eor v1.16b,v1.16b,v18.16b
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#ifndef __ARMEB__
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#ifndef __AARCH64EB__
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rev64 v4.16b,v4.16b
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#endif
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@ -543,7 +543,7 @@ gcm_ghash_v8_4x:
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eor v0.16b,v0.16b,v18.16b
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ext v0.16b,v0.16b,v0.16b,#8
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#ifndef __ARMEB__
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#ifndef __AARCH64EB__
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rev64 v0.16b,v0.16b
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#endif
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st1 {v0.2d},[x0] //write out Xi
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@ -30,7 +30,7 @@ poly1305_init:
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ldp x7,x8,[x1] // load key
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mov x9,#0xfffffffc0fffffff
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movk x9,#0x0fff,lsl#48
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#ifdef __ARMEB__
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#ifdef __AARCH64EB__
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rev x7,x7 // flip bytes
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rev x8,x8
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#endif
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@ -80,7 +80,7 @@ poly1305_blocks:
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.Loop:
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ldp x10,x11,[x1],#16 // load input
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sub x2,x2,#16
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#ifdef __ARMEB__
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#ifdef __AARCH64EB__
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rev x10,x10
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rev x11,x11
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#endif
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@ -148,13 +148,13 @@ poly1305_emit:
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csel x4,x4,x12,eq
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csel x5,x5,x13,eq
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#ifdef __ARMEB__
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#ifdef __AARCH64EB__
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ror x10,x10,#32 // flip nonce words
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ror x11,x11,#32
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#endif
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adds x4,x4,x10 // accumulate nonce
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adc x5,x5,x11
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#ifdef __ARMEB__
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#ifdef __AARCH64EB__
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rev x4,x4 // flip output bytes
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rev x5,x5
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#endif
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@ -277,7 +277,7 @@ poly1305_blocks_neon:
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adcs x5,x5,xzr
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adc x6,x6,xzr
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#ifdef __ARMEB__
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#ifdef __AARCH64EB__
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rev x12,x12
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rev x13,x13
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#endif
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@ -323,7 +323,7 @@ poly1305_blocks_neon:
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ldp x12,x13,[x1],#16 // load input
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sub x2,x2,#16
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add x9,x8,x8,lsr#2 // s1 = r1 + (r1 >> 2)
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#ifdef __ARMEB__
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#ifdef __AARCH64EB__
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rev x12,x12
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rev x13,x13
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#endif
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@ -408,7 +408,7 @@ poly1305_blocks_neon:
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lsl x3,x3,#24
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add x15,x0,#48
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#ifdef __ARMEB__
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#ifdef __AARCH64EB__
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rev x8,x8
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rev x12,x12
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rev x9,x9
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@ -444,7 +444,7 @@ poly1305_blocks_neon:
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ld1 {v4.4s,v5.4s,v6.4s,v7.4s},[x15],#64
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ld1 {v8.4s},[x15]
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#ifdef __ARMEB__
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#ifdef __AARCH64EB__
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rev x8,x8
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rev x12,x12
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rev x9,x9
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@ -505,7 +505,7 @@ poly1305_blocks_neon:
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umull v20.2d,v14.2s,v1.s[2]
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ldp x9,x13,[x16],#48
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umull v19.2d,v14.2s,v0.s[2]
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#ifdef __ARMEB__
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#ifdef __AARCH64EB__
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rev x8,x8
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rev x12,x12
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rev x9,x9
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@ -570,7 +570,7 @@ poly1305_blocks_neon:
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umlal v23.2d,v11.2s,v3.s[0]
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umlal v20.2d,v11.2s,v8.s[0]
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umlal v21.2d,v11.2s,v0.s[0]
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#ifdef __ARMEB__
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#ifdef __AARCH64EB__
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rev x8,x8
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rev x12,x12
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rev x9,x9
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@ -854,13 +854,13 @@ poly1305_emit_neon:
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csel x4,x4,x12,eq
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csel x5,x5,x13,eq
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#ifdef __ARMEB__
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#ifdef __AARCH64EB__
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ror x10,x10,#32 // flip nonce words
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ror x11,x11,#32
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#endif
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adds x4,x4,x10 // accumulate nonce
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adc x5,x5,x11
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#ifdef __ARMEB__
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#ifdef __AARCH64EB__
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rev x4,x4 // flip output bytes
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rev x5,x5
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#endif
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