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Work around a defect in the FIFOEMP status bit of Ultra2 class

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aic7xxx parts.  This problem could result in data corruption
during periods of my PCI bus load by busmasters other than the
aic7xxx.

Many thanks to Andrew Gallatin <gallatin@cs.duke.edu> for characterizing
the symptoms of this problem and testing this fix.
This commit is contained in:
Justin T. Gibbs 1999-09-20 18:57:04 +00:00
parent 236cb8163d
commit 55bad6b5c3
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=51471
1 changed files with 32 additions and 2 deletions
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34
sys/dev/aic7xxx/aic7xxx.seq
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@ -679,7 +679,15 @@ clear_target_state:
* STCNT may have been cleared, so restore it from the residual field.
*/
data_phase_reinit:
if ((ahc->features & AHC_CMD_CHAN) != 0) {
if ((ahc->features & AHC_ULTRA2) != 0) {
/*
* The preload circuitry requires us to
* reload the address too, so pull it from
* the shaddow address.
*/
bmov HADDR, SHADDR, 4;
bmov HCNT, SCB_RESID_DCNT, 3;
} else if ((ahc->features & AHC_CMD_CHAN) != 0) {
bmov STCNT, SCB_RESID_DCNT, 3;
} else {
mvi DINDEX, STCNT;
@ -928,8 +936,30 @@ ultra2_dmafinish:
test DFCNTRL, DIRECTION jnz ultra2_dmahalt;
and DFCNTRL, ~SCSIEN;
test DFCNTRL, SCSIEN jnz .;
ultra2_dmafifoflush:
or DFCNTRL, FIFOFLUSH;
test DFSTATUS, FIFOEMP jz . - 1;
/*
* The FIFOEMP status bit on the Ultra2 class
* of controllers seems to be a bit flaky.
* It appears that if the FIFO is full and the
* transfer ends with some data in the REQ/ACK
* FIFO, FIFOEMP will fall temporarily
* as the data is transferred to the PCI bus.
* This glitch lasts for fewer than 5 clock cycles,
* so we work around the problem by ensuring the
* status bit stays false through a full glitch
* window.
*/
test DFSTATUS, FIFOEMP jz ultra2_dmafifoflush;
test DFSTATUS, FIFOEMP jz ultra2_dmafifoflush;
test DFSTATUS, FIFOEMP jz ultra2_dmafifoflush;
test DFSTATUS, FIFOEMP jz ultra2_dmafifoflush;
test DFSTATUS, FIFOEMP jz ultra2_dmafifoflush;
ultra2_dmafifoempty:
/* Don't clobber an inprogress host data transfer */
test DFSTATUS, MREQPEND jnz ultra2_dmafifoempty;
ultra2_dmahalt:
and DFCNTRL, ~(SCSIEN|HDMAEN);
test DFCNTRL, HDMAEN jnz .;