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arm64: clean up empty lines in .c and .h files

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This commit is contained in:
Mateusz Guzik 2020-09-01 21:18:06 +00:00
parent 654548838b
commit 50cedfede3
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=365069
43 changed files with 3 additions and 110 deletions
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2
sys/arm64/arm64/busdma_bounce.c
View file

@ -411,7 +411,6 @@ bounce_bus_dmamap_destroy(bus_dma_tag_t dmat, bus_dmamap_t map)
return (0);
}
/*
* Allocate a piece of memory that can be efficiently mapped into
* bus device space based on the constraints lited in the dma tag.
@ -840,7 +839,6 @@ bounce_bus_dmamap_load_buffer(bus_dma_tag_t dmat, bus_dmamap_t map, void *buf,
if (map->sync_count == 0 ||
(kvaddr != 0 && kvaddr != sl_vend) ||
(curaddr != sl_pend)) {
if (++map->sync_count > dmat->common.nsegments)
goto cleanup;
sl++;

2
sys/arm64/arm64/freebsd32_machdep.c
View file

@ -116,8 +116,6 @@ freebsd32_sysarch(struct thread *td, struct freebsd32_sysarch_args *uap)
return (EINVAL);
}
#ifdef VFP
static void
get_fpcontext32(struct thread *td, mcontext32_vfp_t *mcp)

1
sys/arm64/arm64/gic_v3_acpi.c
View file

@ -83,7 +83,6 @@ static devclass_t gic_v3_acpi_devclass;
EARLY_DRIVER_MODULE(gic_v3, acpi, gic_v3_acpi_driver, gic_v3_acpi_devclass,
0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE);
struct madt_table_data {
device_t parent;
device_t dev;

1
sys/arm64/arm64/gic_v3_var.h
View file

@ -82,7 +82,6 @@ struct gic_v3_softc {
struct gic_v3_irqsrc *gic_irqs;
};
struct gic_v3_devinfo {
int gic_domain;
int msi_xref;

1
sys/arm64/arm64/gicv3_its.c
View file

@ -1575,7 +1575,6 @@ its_cmd_wait_completion(device_t dev, struct its_cmd *cmd_first,
}
}
static struct its_cmd *
its_cmd_alloc_locked(device_t dev)
{

12
sys/arm64/arm64/identcpu.c
View file

@ -263,7 +263,6 @@ struct mrs_field_value {
MRS_FIELD_VALUE(13ul<< _reg ## _ ## _field ## _SHIFT, "14 "_desc "s"), \
MRS_FIELD_VALUE(14ul<< _reg ## _ ## _field ## _SHIFT, "15 "_desc "s"), \
MRS_FIELD_VALUE(15ul<< _reg ## _ ## _field ## _SHIFT, "16 "_desc "s")
#define MRS_FIELD_VALUE_END { .desc = NULL }
struct mrs_field {
@ -284,7 +283,6 @@ struct mrs_field {
.mask = _register ## _ ## _name ## _MASK, \
.values = (_values), \
}
#define MRS_FIELD_END { .type = MRS_INVALID, }
/* ID_AA64AFR0_EL1 */
@ -292,13 +290,11 @@ static struct mrs_field id_aa64afr0_fields[] = {
MRS_FIELD_END,
};
/* ID_AA64AFR1_EL1 */
static struct mrs_field id_aa64afr1_fields[] = {
MRS_FIELD_END,
};
/* ID_AA64DFR0_EL1 */
static struct mrs_field_value id_aa64dfr0_pmsver[] = {
MRS_FIELD_VALUE(ID_AA64DFR0_PMSVer_NONE, ""),
@ -356,13 +352,11 @@ static struct mrs_field id_aa64dfr0_fields[] = {
MRS_FIELD_END,
};
/* ID_AA64DFR1 */
static struct mrs_field id_aa64dfr1_fields[] = {
MRS_FIELD_END,
};
/* ID_AA64ISAR0_EL1 */
static struct mrs_field_value id_aa64isar0_rndr[] = {
MRS_FIELD_VALUE(ID_AA64ISAR0_RNDR_NONE, ""),
@ -459,7 +453,6 @@ static struct mrs_field id_aa64isar0_fields[] = {
MRS_FIELD_END,
};
/* ID_AA64ISAR1_EL1 */
static struct mrs_field_value id_aa64isar1_i8mm[] = {
MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, I8MM, NONE, IMPL),
@ -556,7 +549,6 @@ static struct mrs_field id_aa64isar1_fields[] = {
MRS_FIELD_END,
};
/* ID_AA64MMFR0_EL1 */
static struct mrs_field_value id_aa64mmfr0_tgran4[] = {
MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, TGran4, NONE, IMPL),
@ -622,7 +614,6 @@ static struct mrs_field id_aa64mmfr0_fields[] = {
MRS_FIELD_END,
};
/* ID_AA64MMFR1_EL1 */
static struct mrs_field_value id_aa64mmfr1_xnx[] = {
MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR1, XNX, NONE, IMPL),
@ -684,7 +675,6 @@ static struct mrs_field id_aa64mmfr1_fields[] = {
MRS_FIELD_END,
};
/* ID_AA64MMFR2_EL1 */
static struct mrs_field_value id_aa64mmfr2_nv[] = {
MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, NV, NONE, IMPL),
@ -735,7 +725,6 @@ static struct mrs_field id_aa64mmfr2_fields[] = {
MRS_FIELD_END,
};
/* ID_AA64PFR0_EL1 */
static struct mrs_field_value id_aa64pfr0_csv3[] = {
MRS_FIELD_VALUE(ID_AA64PFR0_CSV3_NONE, ""),
@ -843,7 +832,6 @@ static struct mrs_field id_aa64pfr0_fields[] = {
MRS_FIELD_END,
};
/* ID_AA64PFR1_EL1 */
static struct mrs_field_value id_aa64pfr1_bt[] = {
MRS_FIELD_VALUE(ID_AA64PFR1_BT_NONE, ""),

1
sys/arm64/arm64/machdep.c
View file

@ -410,7 +410,6 @@ set_regs32(struct thread *td, struct reg32 *regs)
tf->tf_elr = regs->r_pc;
tf->tf_spsr = regs->r_cpsr;
return (0);
}

2
sys/arm64/arm64/machdep_boot.c
View file

@ -55,7 +55,6 @@ extern int *end;
static char *loader_envp;
static char static_kenv[4096];
#ifdef FDT
#define CMDLINE_GUARD "FreeBSD:"
#define LBABI_MAX_COMMAND_LINE 512
@ -79,7 +78,6 @@ static char linux_command_line[LBABI_MAX_COMMAND_LINE + 1];
size = roundup(size, sizeof(u_long)); \
} while (0)
/* Build minimal set of metatda. */
static vm_offset_t
fake_preload_metadata(void *dtb_ptr, size_t dtb_size)

2
sys/arm64/arm64/nexus.c
View file

@ -209,7 +209,6 @@ nexus_add_child(device_t bus, u_int order, const char *name, int unit)
return (child);
}
/*
* Allocate a resource on behalf of child. NB: child is usually going to be a
* child of one of our descendants, not a direct child of nexus0.
@ -398,7 +397,6 @@ nexus_set_resource(device_t dev, device_t child, int type, int rid,
return(0);
}
static int
nexus_deactivate_resource(device_t bus, device_t child, int type, int rid,
struct resource *r)

5
sys/arm64/arm64/pmap.c
View file

@ -600,7 +600,6 @@ pmap_l3_valid(pt_entry_t l3)
return ((l3 & ATTR_DESCR_MASK) == L3_PAGE);
}
CTASSERT(L1_BLOCK == L2_BLOCK);
static pt_entry_t
@ -1422,7 +1421,6 @@ pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
return PHYS_TO_DMAP(start);
}
/*
* Add a list of wired pages to the kva
* this routine is only used for temporary
@ -2060,7 +2058,6 @@ pmap_growkernel(vm_offset_t addr)
}
}
/***************************************************
* page management routines.
***************************************************/
@ -2883,7 +2880,6 @@ pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
lock = NULL;
for (; sva < eva; sva = va_next) {
if (pmap->pm_stats.resident_count == 0)
break;
@ -3137,7 +3133,6 @@ pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
PMAP_LOCK(pmap);
for (; sva < eva; sva = va_next) {
l0 = pmap_l0(pmap, sva);
if (pmap_load(l0) == 0) {
va_next = (sva + L0_SIZE) & ~L0_OFFSET;

2
sys/arm64/arm64/sys_machdep.c
View file

@ -37,11 +37,9 @@ __FBSDID("$FreeBSD$");
#include <machine/sysarch.h>
int
sysarch(struct thread *td, struct sysarch_args *uap)
{
return (ENOTSUP);
}

1
sys/arm64/arm64/vfp.c
View file

@ -218,7 +218,6 @@ vfp_restore_state(void)
* cpu we need to restore the old state.
*/
if (PCPU_GET(fpcurthread) != curthread || cpu != curpcb->pcb_vfpcpu) {
vfp_restore(curthread->td_pcb->pcb_fpusaved);
PCPU_SET(fpcurthread, curthread);
curpcb->pcb_vfpcpu = cpu;

2
sys/arm64/broadcom/genet/if_genet.c
View file

@ -99,7 +99,6 @@ __FBSDID("$FreeBSD$");
#define TX_NEXT(n, count) (((n) + 1) & ((count) - 1))
#define RX_NEXT(n, count) (((n) + 1) & ((count) - 1))
#define TX_MAX_SEGS 20
/* Maximum number of mbufs to send to if_input */
@ -1259,7 +1258,6 @@ gen_intr(void *arg)
if (val & GENET_IRQ_RXDMA_DONE)
gen_rxintr(sc, &sc->rx_queue[DEF_RXQUEUE]);
if (val & GENET_IRQ_TXDMA_DONE) {
gen_txintr(sc, &sc->tx_queue[DEF_TXQUEUE]);
if (!if_sendq_empty(sc->ifp))

1
sys/arm64/cavium/thunder_pcie_common.c
View file

@ -185,7 +185,6 @@ thunder_pcie_alloc_resource(device_t dev, device_t child, int type, int *rid,
*/
if (((type == SYS_RES_IOPORT) || (type == SYS_RES_MEMORY)) &&
RMAN_IS_DEFAULT_RANGE(start, end)) {
/* Read BAR manually to get resource address and size */
pci_read_bar(child, *rid, &map, &testval, NULL);

1
sys/arm64/cavium/thunder_pcie_fdt.c
View file

@ -90,7 +90,6 @@ DRIVER_MODULE(thunder_pcib, simplebus, thunder_pcie_fdt_driver,
DRIVER_MODULE(thunder_pcib, ofwbus, thunder_pcie_fdt_driver,
thunder_pcie_fdt_devclass, 0, 0);
static int
thunder_pcie_fdt_probe(device_t dev)
{

2
sys/arm64/cavium/thunder_pcie_pem.c
View file

@ -648,7 +648,6 @@ thunder_pem_alloc_resource(device_t dev, device_t child, int type, int *rid,
end, count, flags));
}
if (!RMAN_IS_DEFAULT_RANGE(start, end)) {
/*
* We might get PHYS addresses here inherited from EFI.
@ -658,7 +657,6 @@ thunder_pem_alloc_resource(device_t dev, device_t child, int type, int *rid,
start = range_addr_phys_to_pci(sc->ranges, start);
end = start + count - 1;
}
}
if (bootverbose) {

1
sys/arm64/coresight/coresight_etm4x.c
View file

@ -256,7 +256,6 @@ etm_attach(device_t dev)
}
static device_method_t etm_methods[] = {
/* Coresight interface */
DEVMETHOD(coresight_init, etm_init),
DEVMETHOD(coresight_enable, etm_enable),

1
sys/arm64/coresight/coresight_fdt.c
View file

@ -71,7 +71,6 @@ coresight_fdt_get_ports(phandle_t dev_node,
if (strcasecmp(name, "port") ||
strncasecmp(name, "port@", 6)) {
port_reg = -1;
OF_getencprop(child, "reg", (void *)&port_reg,
sizeof(port_reg));

2
sys/arm64/freescale/imx/clk/imx_clk_mux.c
View file

@ -29,7 +29,6 @@
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/conf.h>
#include <sys/bus.h>
@ -74,7 +73,6 @@ static clknode_method_t imx_clk_mux_methods[] = {
DEFINE_CLASS_1(imx_clk_mux, imx_clk_mux_class, imx_clk_mux_methods,
sizeof(struct imx_clk_mux_sc), clknode_class);
static int
imx_clk_mux_init(struct clknode *clk, device_t dev)
{

2
sys/arm64/freescale/imx/imx7gpc.c
View file

@ -142,7 +142,6 @@ imx7gpc_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
PIC_PRE_ITHREAD(sc->parent, isrc);
}
static void
imx7gpc_post_ithread(device_t dev, struct intr_irqsrc *isrc)
{
@ -207,7 +206,6 @@ imx7gpc_attach(device_t dev)
return (ENXIO);
}
i = 0;
sc->memres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &i,
RF_ACTIVE);

2
sys/arm64/freescale/imx/imx8mq_ccm.c
View file

@ -134,7 +134,7 @@ static struct imx_clk imx_clks[] = {
FIXED(IMX8MQ_SYS1_PLL_OUT, "sys1_pll_out", 800000000),
FIXED(IMX8MQ_SYS2_PLL_OUT, "sys2_pll_out", 1000000000),
SSCG_PLL(IMX8MQ_SYS3_PLL_OUT, "sys3_pll_out", sys3_pll_out_p, 0x48),
MUX(IMX8MQ_ARM_PLL_REF_SEL, "arm_pll_ref_sel", pll_ref_p, 0, 0x28, 16, 2),
MUX(IMX8MQ_GPU_PLL_REF_SEL, "gpu_pll_ref_sel", pll_ref_p, 0, 0x18, 16, 2),
MUX(IMX8MQ_VPU_PLL_REF_SEL, "vpu_pll_ref_sel", pll_ref_p, 0, 0x20, 16, 2),

1
sys/arm64/include/acpica_machdep.h
View file

@ -36,7 +36,6 @@
#ifndef __ACPICA_MACHDEP_H__
#define __ACPICA_MACHDEP_H__
#ifdef _KERNEL
#include <machine/_bus.h>

1
sys/arm64/include/armreg.h
View file

@ -164,7 +164,6 @@
(ISS_MSR_OP0_MASK | ISS_MSR_OP2_MASK | ISS_MSR_OP1_MASK | \
ISS_MSR_CRn_MASK | ISS_MSR_CRm_MASK)
#define ISS_DATA_ISV_SHIFT 24
#define ISS_DATA_ISV (0x01 << ISS_DATA_ISV_SHIFT)
#define ISS_DATA_SAS_SHIFT 22

12
sys/arm64/include/bus.h
View file

@ -261,7 +261,6 @@ struct bus_space {
bus_size_t, const u_int64_t *, bus_size_t);
};
/*
* Utility macros; INTERNAL USE ONLY.
*/
@ -287,7 +286,6 @@ struct bus_space {
#define __bs_nonsingle_s(type, sz, t, h, o, a, c) \
(*(t)->__bs_opname_s(type,sz))((t)->bs_cookie, h, o, a, c)
/*
* Mapping and unmapping operations.
*/
@ -298,7 +296,6 @@ struct bus_space {
#define bus_space_subregion(t, h, o, s, hp) \
(*(t)->bs_subregion)((t)->bs_cookie, (h), (o), (s), (hp))
/*
* Allocation and deallocation operations.
*/
@ -314,8 +311,6 @@ struct bus_space {
#define bus_space_barrier(t, h, o, l, f) \
(*(t)->bs_barrier)((t)->bs_cookie, (h), (o), (l), (f))
/*
* Bus read (single) operations.
*/
@ -350,7 +345,6 @@ struct bus_space {
#define bus_space_read_multi_stream_8(t, h, o, a, c) \
__bs_nonsingle_s(rm,8,(t),(h),(o),(a),(c))
/*
* Bus read region operations.
*/
@ -372,7 +366,6 @@ struct bus_space {
#define bus_space_read_region_stream_8(t, h, o, a, c) \
__bs_nonsingle_s(rr,8,(t),(h),(o),(a),(c))
/*
* Bus write (single) operations.
*/
@ -386,7 +379,6 @@ struct bus_space {
#define bus_space_write_stream_4(t, h, o, v) __bs_ws_s(4,(t),(h),(o),(v))
#define bus_space_write_stream_8(t, h, o, v) __bs_ws_s(8,(t),(h),(o),(v))
/*
* Bus write multiple operations.
*/
@ -408,7 +400,6 @@ struct bus_space {
#define bus_space_write_multi_stream_8(t, h, o, a, c) \
__bs_nonsingle_s(wm,8,(t),(h),(o),(a),(c))
/*
* Bus write region operations.
*/
@ -430,7 +421,6 @@ struct bus_space {
#define bus_space_write_region_stream_8(t, h, o, a, c) \
__bs_nonsingle_s(wr,8,(t),(h),(o),(a),(c))
/*
* Set multiple operations.
*/
@ -443,7 +433,6 @@ struct bus_space {
#define bus_space_set_multi_8(t, h, o, v, c) \
__bs_set(sm,8,(t),(h),(o),(v),(c))
/*
* Set region operations.
*/
@ -456,7 +445,6 @@ struct bus_space {
#define bus_space_set_region_8(t, h, o, v, c) \
__bs_set(sr,8,(t),(h),(o),(v),(c))
/*
* Copy operations.
*/

1
sys/arm64/include/cpu.h
View file

@ -157,7 +157,6 @@
#define CPU_MATCH_ERRATA_CAVIUM_THUNDERX_1_1 0
#endif
extern char btext[];
extern char etext[];

4
sys/arm64/include/endian.h
View file

@ -66,7 +66,7 @@ __bswap64(__uint64_t x)
__asm __volatile("rev %0, %1\n"
: "=&r" (ret), "+r" (x));
return (ret);
}
@ -77,7 +77,7 @@ __bswap32_var(__uint32_t v)
__asm __volatile("rev32 %x0, %x1\n"
: "=&r" (ret), "+r" (v));
return (ret);
}

1
sys/arm64/include/ieeefp.h
View file

@ -40,5 +40,4 @@ extern fp_except_t fpgetmask(void);
extern fp_except_t fpsetmask(fp_except_t);
__END_DECLS
#endif /* _MACHINE_IEEEFP_H_ */

1
sys/arm64/include/ucontext.h
View file

@ -86,5 +86,4 @@ typedef struct __mcontext32_vfp {
#endif /* COMPAT_FREEBSD32 */
#endif /* !_MACHINE_UCONTEXT_H_ */

1
sys/arm64/include/vfp.h
View file

@ -32,7 +32,6 @@
#ifndef _MACHINE_VFP_H_
#define _MACHINE_VFP_H_
#ifndef LOCORE
struct vfpstate {
__uint128_t vfp_regs[32];

6
sys/arm64/linux/linux_proto.h
View file

@ -1343,42 +1343,36 @@ int linux_pkey_free(struct thread *, struct linux_pkey_free_args *);
#endif /* COMPAT_43 */
#ifdef COMPAT_FREEBSD4
#define nosys linux_nosys
#endif /* COMPAT_FREEBSD4 */
#ifdef COMPAT_FREEBSD6
#define nosys linux_nosys
#endif /* COMPAT_FREEBSD6 */
#ifdef COMPAT_FREEBSD7
#define nosys linux_nosys
#endif /* COMPAT_FREEBSD7 */
#ifdef COMPAT_FREEBSD10
#define nosys linux_nosys
#endif /* COMPAT_FREEBSD10 */
#ifdef COMPAT_FREEBSD11
#define nosys linux_nosys
#endif /* COMPAT_FREEBSD11 */
#ifdef COMPAT_FREEBSD12
#define nosys linux_nosys

1
sys/arm64/qoriq/clk/qoriq_clk_pll.h
View file

@ -50,4 +50,3 @@ int qoriq_clk_pll_register(struct clkdom *clkdom,
const struct qoriq_clk_pll_def *clkdef);
#endif /* _QORIQ_CLK_PLL_H_ */

1
sys/arm64/qoriq/ls1046_gpio.c
View file

@ -109,7 +109,6 @@ static int qoriq_gpio_pin_access_32(device_t, uint32_t, uint32_t, uint32_t,
uint32_t*);
static int qoriq_gpio_pin_config_32(device_t, uint32_t, uint32_t, uint32_t*);
static device_method_t qoriq_gpio_methods[] = {
DEVMETHOD(device_probe, qoriq_gpio_probe),
DEVMETHOD(device_attach, qoriq_gpio_attach),

12
sys/arm64/rockchip/clk/rk3399_cru.c
View file

@ -55,7 +55,6 @@ __FBSDID("$FreeBSD$");
#define CRU_CLKSEL_CON(x) (0x100 + (x) * 0x4)
#define CRU_CLKGATE_CON(x) (0x300 + (x) * 0x4)
/* GATES */
static struct rk_cru_gate rk3399_gates[] = {
@ -106,7 +105,6 @@ static struct rk_cru_gate rk3399_gates[] = {
GATE(0, "clk_ddrc_bpll_src", "bpll", 3, 1),
GATE(0, "clk_ddrc_lpll_src", "lpll", 3, 0),
/* CRU_CLKGATE_CON4 */
/* 15 - 12 unused */
GATE(SCLK_PVTM_DDR, "clk_pvtm_ddr", "xin24m", 4, 11),
@ -219,7 +217,6 @@ static struct rk_cru_gate rk3399_gates[] = {
GATE(SCLK_I2C5, "clk_i2c5", "clk_i2c5_c", 10, 1),
GATE(SCLK_I2C1, "clk_i2c1", "clk_i2c1_c", 10, 0),
/* CRU_CLKGATE_CON11 */
GATE(SCLK_MIPIDPHY_CFG, "clk_mipidphy_cfg", "xin24m", 11, 15),
GATE(SCLK_MIPIDPHY_REF, "clk_mipidphy_ref", "xin24m", 11, 14),
@ -311,7 +308,6 @@ static struct rk_cru_gate rk3399_gates[] = {
GATE(ACLK_IEP_NOC, "aclk_iep_noc", "aclk_iep_pre", 16, 1),
GATE(ACLK_IEP, "aclk_iep", "aclk_iep_pre", 16, 0),
/* CRU_CLKGATE_CON17 */
/* 15 - 12 unused */
GATE(HCLK_VDU_NOC, "hclk_vdu_noc", "hclk_vdu_pre", 17, 11),
@ -346,7 +342,6 @@ static struct rk_cru_gate rk3399_gates[] = {
GATE(ACLK_CENTER_PERI_NOC, "aclk_center_peri_noc", "aclk_center", 19, 1),
GATE(ACLK_CENTER_MAIN_NOC, "aclk_center_main_noc", "aclk_center", 19, 0),
/* CRU_CLKGATE_CON20 */
GATE(0, "hclk_ahb1tom", "hclk_perihp", 20, 15),
GATE(0, "pclk_perihp_noc", "pclk_perihp", 20, 14),
@ -376,7 +371,6 @@ static struct rk_cru_gate rk3399_gates[] = {
GATE(SCLK_DPHY_TX0_CFG, "clk_dphy_tx0_cfg", "clk_mipidphy_cfg", 21, 1),
GATE(SCLK_DPHY_PLL, "clk_dphy_pll", "clk_mipidphy_ref", 21, 0),
/* CRU_CLKGATE_CON22 */
GATE(PCLK_EFUSE1024S, "pclk_efuse1024s", "pclk_perilp1", 22, 15),
GATE(PCLK_EFUSE1024NS, "pclk_efuse1024ns", "pclk_perilp1", 22, 14),
@ -690,7 +684,6 @@ static struct rk_clk_armclk_rates rk3399_cpu_b_rates[] = {
{ 96000000, 1},
};
/* Standard PLL. */
#define PLL(_id, _name, _base) \
{ \
@ -739,7 +732,6 @@ PLIST(dclk_vop1_p)= {"dclk_vop1_div", "dclk_vop1_frac"};
PLIST(clk_cif_p) = {"clk_cifout_src", "xin24m"};
PLIST(pll_src_24m_usbphy480m_p) = { "xin24m", "clk_usbphy_480m"};
PLIST(pll_src_24m_pciephy_p) = { "xin24m", "clk_pciephy_ref100m"};
PLIST(pll_src_24m_32k_cpll_gpll_p)= {"xin24m", "xin32k", "cpll", "gpll"};
@ -781,7 +773,6 @@ PLIST(uart2_p)= {"clk_uart2_div", "clk_uart2_frac", "xin24m"};
PLIST(uart3_p)= {"clk_uart3_div", "clk_uart3_frac", "xin24m"};
static struct rk_clk rk3399_clks[] = {
/* External clocks */
LINK("xin24m"),
FRATE(0, "xin32k", 32768),
@ -1063,7 +1054,6 @@ static struct rk_clk rk3399_clks[] = {
COMP(0, "aclk_vio_c", pll_src_cpll_gpll_ppll_p, 0,
42, 0, 5, 6, 2),
/* CRU_CLKSEL_CON43 */
CDIV(0, "pclk_hdcp_c", "aclk_hdcp", 0,
43, 10, 5),
@ -1229,8 +1219,6 @@ static struct rk_clk rk3399_clks[] = {
* MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio", RK3399_SDIO_CON1, 1),
*/
};
static int

1
sys/arm64/rockchip/clk/rk3399_pmucru.c
View file

@ -729,7 +729,6 @@ static struct rk_clk_composite_def pclk_pmu_src = {
.div_width = 5,
};
#define SCLK_I2C0_PMU 9
#define SCLK_I2C4_PMU 10
#define SCLK_I2C8_PMU 11

1
sys/arm64/rockchip/clk/rk_clk_fract.c
View file

@ -71,7 +71,6 @@ static clknode_method_t rk_clk_fract_methods[] = {
DEFINE_CLASS_1(rk_clk_fract, rk_clk_fract_class, rk_clk_fract_methods,
sizeof(struct rk_clk_fract_sc), clknode_class);
/*
* Compute best rational approximation of input fraction
* for fixed sized fractional divider registers.

2
sys/arm64/rockchip/clk/rk_clk_mux.c
View file

@ -29,7 +29,6 @@
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/conf.h>
#include <sys/bus.h>
@ -75,7 +74,6 @@ static clknode_method_t rk_clk_mux_methods[] = {
DEFINE_CLASS_1(rk_clk_mux, rk_clk_mux_class, rk_clk_mux_methods,
sizeof(struct rk_clk_mux_sc), clknode_class);
static int
rk_clk_mux_init(struct clknode *clk, device_t dev)
{

1
sys/arm64/rockchip/rk805reg.h
View file

@ -27,7 +27,6 @@
* $FreeBSD$
*/
#ifndef _RK805REG_H_
#define _RK805REG_H_

1
sys/arm64/rockchip/rk_dwc3.c
View file

@ -41,7 +41,6 @@ __FBSDID("$FreeBSD$");
#include <sys/gpio.h>
#include <machine/bus.h>
#include <dev/fdt/simplebus.h>
#include <dev/fdt/fdt_common.h>

2
sys/arm64/rockchip/rk_i2c.c
View file

@ -46,7 +46,6 @@ __FBSDID("$FreeBSD$");
#include "iicbus_if.h"
#define RK_I2C_CON 0x00
#define RK_I2C_CON_EN (1 << 0)
#define RK_I2C_CON_MODE_SHIFT 1
@ -238,7 +237,6 @@ rk_i2c_fill_tx(struct rk_i2c_softc *sc)
sc->cnt++;
}
buf32 |= buf << (j * 8);
}
RK_I2C_WRITE(sc, RK_I2C_TXDATA_BASE + 4 * i, buf32);

9
sys/arm64/rockchip/rk_pcie.c
View file

@ -203,7 +203,6 @@ struct rk_pcie_softc {
phandle_t node;
struct mtx mtx;
struct ofw_pci_range mem_range;
struct ofw_pci_range pref_mem_range;
struct ofw_pci_range io_range;
@ -245,7 +244,6 @@ static struct ofw_compat_data compat_data[] = {
{NULL, 0},
};
static uint32_t
rk_pcie_local_cfg_read(struct rk_pcie_softc *sc, bool priv, u_int reg,
int bytes)
@ -305,7 +303,6 @@ rk_pcie_local_cfg_write(struct rk_pcie_softc *sc, bool priv, u_int reg,
}
}
static bool
rk_pcie_check_dev(struct rk_pcie_softc *sc, u_int bus, u_int slot, u_int func,
u_int reg)
@ -334,7 +331,6 @@ rk_pcie_check_dev(struct rk_pcie_softc *sc, u_int bus, u_int slot, u_int func,
return (true);
}
static void
rk_pcie_map_out_atu(struct rk_pcie_softc *sc, int idx, int type,
int num_bits, uint64_t pa)
@ -342,7 +338,6 @@ rk_pcie_map_out_atu(struct rk_pcie_softc *sc, int idx, int type,
uint32_t addr0;
uint64_t max_size;
/* Check HW constrains */
max_size = idx == 0 ? ATU_OB_REGION_0_SIZE: ATU_OB_REGION_SIZE;
KASSERT(idx < ATU_OB_REGIONS, ("Invalid region index: %d\n", idx));
@ -1027,7 +1022,6 @@ rk_pcie_setup_sw(struct rk_pcie_softc *sc)
pcib_bridge_init(sc->dev);
/* Setup config registers */
APB_WR4(sc, PCIE_CORE_CONFIG_VENDOR, 0x1D87); /* Rockchip vendor ID*/
PRIV_CFG_WR1(sc, PCIR_CLASS, PCIC_BRIDGE);
@ -1137,7 +1131,6 @@ rk_pcie_legacy_irq(void *arg)
return (FILTER_STRAY);
}
static bus_dma_tag_t
rk_pcie_get_dma_tag(device_t dev, device_t child)
{
@ -1147,7 +1140,6 @@ rk_pcie_get_dma_tag(device_t dev, device_t child)
return (sc->dmat);
}
static int
rk_pcie_probe(device_t dev)
{
@ -1370,7 +1362,6 @@ rk_pcie_attach(device_t dev)
return (rv);
}
static device_method_t rk_pcie_methods[] = {
/* Device interface */
DEVMETHOD(device_probe, rk_pcie_probe),

5
sys/arm64/rockchip/rk_pcie_phy.c
View file

@ -73,7 +73,6 @@ __FBSDID("$FreeBSD$");
#define PHY_CFG_SCC_LOCK 0x12
#define CLK_SCC_100M_GATE (1 << 2)
#define STATUS1_PLL_LOCKED (1 << 9)
static struct ofw_compat_data compat_data[] = {
@ -81,7 +80,6 @@ static struct ofw_compat_data compat_data[] = {
{NULL, 0}
};
struct rk_pcie_phy_softc {
device_t dev;
struct syscon *syscon;
@ -99,14 +97,12 @@ struct rk_pcie_phy_softc {
#define PHY_ASSERT_LOCKED(_sc) mtx_assert(&(_sc)->mtx, MA_OWNED);
#define PHY_ASSERT_UNLOCKED(_sc) mtx_assert(&(_sc)->mtx, MA_NOTOWNED);
#define RD4(sc, reg) SYSCON_READ_4((sc)->syscon, (reg))
#define WR4(sc, reg, mask, val) \
SYSCON_WRITE_4((sc)->syscon, (reg), ((mask) << GRF_HIWORD_SHIFT) | (val))
#define MAX_LANE 4
static void
cfg_write(struct rk_pcie_phy_softc *sc, uint32_t reg, uint32_t data)
{
@ -255,7 +251,6 @@ rk_pcie_phy_enable(struct phynode *phynode, bool enable)
return (rv);
}
/* Phy class and methods. */
static int rk_pcie_phy_enable(struct phynode *phynode, bool enable);
static phynode_method_t rk_pcie_phy_phynode_methods[] = {

2
sys/arm64/rockchip/rk_pinctrl.c
View file

@ -87,7 +87,6 @@ struct rk_pinctrl_gpio {
device_t gpio_dev;
};
struct rk_pinctrl_softc;
struct rk_pinctrl_conf {
@ -468,7 +467,6 @@ static struct rk_pinctrl_pin_fixup rk3328_pin_fixup[] = {
RK_PINFIX(2, 23, 0x30, 14, 0x6000),
};
static struct rk_pinctrl_pin_drive rk3328_pin_drive[] = {
/* bank sub offs val ma */
RK_PINDRIVE(0, 0, 0x200, 0, 2),

1
sys/arm64/rockchip/rk_tsadc.c
View file

@ -387,7 +387,6 @@ tsadc_raw_to_temp(struct tsadc_softc *sc, uint32_t raw)
}
}
/*
* Translated value is between i and i - 1 table entries.
* Do linear interpolation for it.