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Fix EXCP_MASK to include all relevant bits from scause.

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While cause codes higher than 16 are reserved, the exception code
field of the register is defined to be all bits but the upper-most
bit.

Reviewed by:	mhorne
MFC after:	1 week
Sponsored by:	DARPA
Differential Revision:	https://reviews.freebsd.org/D23510
This commit is contained in:
John Baldwin 2020-02-05 20:34:22 +00:00
parent ac2b208d08
commit 4a9b01b262
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=357595
1 changed files with 1 additions and 2 deletions
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3
sys/riscv/include/riscvreg.h
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@ -37,8 +37,7 @@
#ifndef _MACHINE_RISCVREG_H_
#define _MACHINE_RISCVREG_H_
#define EXCP_SHIFT 0
#define EXCP_MASK (0xf << EXCP_SHIFT)
#define EXCP_MASK (~EXCP_INTR)
#define EXCP_MISALIGNED_FETCH 0
#define EXCP_FAULT_FETCH 1
#define EXCP_ILLEGAL_INSTRUCTION 2