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https://github.com/freebsd/freebsd-src
synced 2024-10-15 04:43:53 +00:00
- Make tables, device ID strings etc const.
- Use NULL instead of 0 for pointers. - Remove redundant bzero(9)'ing of the softc. - Remove redundant/unused softc members. - Don't allocate MSI/MSI-X as RF_SHAREABLE. - Re-use bus accessor macros instead of duplicating them. - In bce_miibus_{read,write}_reg(), remove superfluous limiting of the PHY address (missed in r213893). MFC after: 1 week
This commit is contained in:
parent
1f9d53d893
commit
499e58864a
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=247565
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@ -95,7 +95,7 @@ __FBSDID("$FreeBSD$");
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/****************************************************************************/
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#define BCE_DEVDESC_MAX 64
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static struct bce_type bce_devs[] = {
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static const struct bce_type bce_devs[] = {
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/* BCM5706C Controllers and OEM boards. */
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{ BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3101,
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"HP NC370T Multifunction Gigabit Server Adapter" },
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@ -161,7 +161,7 @@ static struct bce_type bce_devs[] = {
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/****************************************************************************/
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/* Supported Flash NVRAM device data. */
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/****************************************************************************/
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static struct flash_spec flash_table[] =
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static const struct flash_spec flash_table[] =
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{
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#define BUFFERED_FLAGS (BCE_NV_BUFFERED | BCE_NV_TRANSLATE)
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#define NONBUFFERED_FLAGS (BCE_NV_WREN)
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@ -258,7 +258,7 @@ static struct flash_spec flash_table[] =
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* logical-to-physical mapping is required in the
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* driver.
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*/
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static struct flash_spec flash_5709 = {
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static const struct flash_spec flash_5709 = {
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.flags = BCE_NV_BUFFERED,
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.page_bits = BCM5709_FLASH_PAGE_BITS,
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.page_size = BCM5709_FLASH_PAGE_SIZE,
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@ -481,8 +481,8 @@ MODULE_DEPEND(bce, pci, 1, 1, 1);
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MODULE_DEPEND(bce, ether, 1, 1, 1);
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MODULE_DEPEND(bce, miibus, 1, 1, 1);
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DRIVER_MODULE(bce, pci, bce_driver, bce_devclass, 0, 0);
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DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, 0, 0);
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DRIVER_MODULE(bce, pci, bce_driver, bce_devclass, NULL, NULL);
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DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, NULL, NULL);
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/****************************************************************************/
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@ -647,7 +647,7 @@ SYSCTL_UINT(_hw_bce, OID_AUTO, rx_ticks, CTLFLAG_RDTUN,
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static int
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bce_probe(device_t dev)
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{
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struct bce_type *t;
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const struct bce_type *t;
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struct bce_softc *sc;
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char *descbuf;
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u16 vid = 0, did = 0, svid = 0, sdid = 0;
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@ -655,7 +655,6 @@ bce_probe(device_t dev)
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t = bce_devs;
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sc = device_get_softc(dev);
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bzero(sc, sizeof(struct bce_softc));
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sc->bce_unit = device_get_unit(dev);
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sc->bce_dev = dev;
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@ -1040,7 +1039,7 @@ bce_attach(device_t dev)
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struct bce_softc *sc;
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struct ifnet *ifp;
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u32 val;
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int error, rid, rc = 0;
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int count, error, rc = 0, rid;
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sc = device_get_softc(dev);
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sc->bce_dev = dev;
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@ -1084,14 +1083,14 @@ bce_attach(device_t dev)
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((sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
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&rid, RF_ACTIVE)) != NULL)) {
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msi_needed = sc->bce_msi_count = 1;
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msi_needed = count = 1;
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if (((error = pci_alloc_msix(dev, &sc->bce_msi_count)) != 0) ||
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(sc->bce_msi_count != msi_needed)) {
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if (((error = pci_alloc_msix(dev, &count)) != 0) ||
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(count != msi_needed)) {
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BCE_PRINTF("%s(%d): MSI-X allocation failed! Requested = %d,"
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"Received = %d, error = %d\n", __FILE__, __LINE__,
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msi_needed, sc->bce_msi_count, error);
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sc->bce_msi_count = 0;
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msi_needed, count, error);
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count = 0;
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pci_release_msi(dev);
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bus_release_resource(dev, SYS_RES_MEMORY, rid,
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sc->bce_res_irq);
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@ -1100,19 +1099,18 @@ bce_attach(device_t dev)
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DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI-X interrupt.\n",
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__FUNCTION__);
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sc->bce_flags |= BCE_USING_MSIX_FLAG;
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sc->bce_intr = bce_intr;
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}
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}
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#endif
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/* Try allocating a MSI interrupt. */
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if ((sc->bce_cap_flags & BCE_MSI_CAPABLE_FLAG) &&
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(bce_msi_enable >= 1) && (sc->bce_msi_count == 0)) {
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sc->bce_msi_count = 1;
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if ((error = pci_alloc_msi(dev, &sc->bce_msi_count)) != 0) {
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(bce_msi_enable >= 1) && (count == 0)) {
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count = 1;
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if ((error = pci_alloc_msi(dev, &count)) != 0) {
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BCE_PRINTF("%s(%d): MSI allocation failed! "
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"error = %d\n", __FILE__, __LINE__, error);
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sc->bce_msi_count = 0;
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count = 0;
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pci_release_msi(dev);
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} else {
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DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI "
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@ -1120,23 +1118,19 @@ bce_attach(device_t dev)
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sc->bce_flags |= BCE_USING_MSI_FLAG;
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if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709)
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sc->bce_flags |= BCE_ONE_SHOT_MSI_FLAG;
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sc->bce_irq_rid = 1;
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sc->bce_intr = bce_intr;
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rid = 1;
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}
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}
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/* Try allocating a legacy interrupt. */
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if (sc->bce_msi_count == 0) {
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if (count == 0) {
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DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using INTx interrupt.\n",
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__FUNCTION__);
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rid = 0;
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sc->bce_intr = bce_intr;
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}
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sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
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&rid, RF_SHAREABLE | RF_ACTIVE);
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sc->bce_irq_rid = rid;
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&rid, RF_ACTIVE | (count != 0 ? 0 : RF_SHAREABLE));
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/* Report any IRQ allocation errors. */
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if (sc->bce_res_irq == NULL) {
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@ -1635,7 +1629,7 @@ bce_shutdown(device_t dev)
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static u32
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bce_reg_rd(struct bce_softc *sc, u32 offset)
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{
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u32 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, offset);
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u32 val = REG_RD(sc, offset);
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DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n",
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__FUNCTION__, offset, val);
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return val;
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@ -1653,7 +1647,7 @@ bce_reg_wr16(struct bce_softc *sc, u32 offset, u16 val)
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{
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DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%04X\n",
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__FUNCTION__, offset, val);
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bus_space_write_2(sc->bce_btag, sc->bce_bhandle, offset, val);
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REG_WR16(sc, offset, val);
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}
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@ -1668,7 +1662,7 @@ bce_reg_wr(struct bce_softc *sc, u32 offset, u32 val)
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{
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DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n",
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__FUNCTION__, offset, val);
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bus_space_write_4(sc->bce_btag, sc->bce_bhandle, offset, val);
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REG_WR(sc, offset, val);
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}
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#endif
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@ -1879,13 +1873,6 @@ bce_miibus_read_reg(device_t dev, int phy, int reg)
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sc = device_get_softc(dev);
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/* Make sure we are accessing the correct PHY address. */
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if (phy != sc->bce_phy_addr) {
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DBPRINT(sc, BCE_INSANE_PHY, "Invalid PHY address %d "
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"for PHY read!\n", phy);
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return(0);
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}
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/*
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* The 5709S PHY is an IEEE Clause 45 PHY
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* with special mappings to work with IEEE
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sc = device_get_softc(dev);
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/* Make sure we are accessing the correct PHY address. */
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if (phy != sc->bce_phy_addr) {
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DBPRINT(sc, BCE_INSANE_PHY, "Invalid PHY address %d "
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"for PHY write!\n", phy);
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return(0);
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}
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DB_PRINT_PHY_REG(reg, val);
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/*
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{
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u32 val;
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int j, entry_count, rc = 0;
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struct flash_spec *flash;
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const struct flash_spec *flash;
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DBENTER(BCE_VERBOSE_NVRAM);
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if (sc->bce_res_irq != NULL) {
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DBPRINT(sc, BCE_INFO_RESET, "Releasing IRQ.\n");
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bus_release_resource(dev, SYS_RES_IRQ, sc->bce_irq_rid,
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sc->bce_res_irq);
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bus_release_resource(dev, SYS_RES_IRQ,
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rman_get_rid(sc->bce_res_irq), sc->bce_res_irq);
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}
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if (sc->bce_flags & (BCE_USING_MSI_FLAG | BCE_USING_MSIX_FLAG)) {
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return;
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}
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#endif
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@ -622,7 +622,7 @@ struct bce_type {
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u_int16_t bce_did;
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u_int16_t bce_svid;
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u_int16_t bce_sdid;
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char *bce_name;
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const char *bce_name;
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};
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/****************************************************************************/
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u32 page_size;
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u32 addr_mask;
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u32 total_size;
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u8 *name;
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const u8 *name;
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};
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@ -2001,7 +2001,7 @@ struct l2_fhdr {
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#define BCE_MISC_ENABLE_CLR_BITS_UMP_ENABLE (1L<<27)
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#define BCE_MISC_ENABLE_CLR_BITS_RV2P_CMD_SCHEDULER_ENABLE (1L<<28)
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#define BCE_MISC_ENABLE_CLR_BITS_RSVD_FUTURE_ENABLE (0x7L<<29)
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#define BCE_MISC_ENABLE_CLR_DEFAULT 0x17ffffff
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#define BCE_MISC_CLOCK_CONTROL_BITS 0x00000818
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u32 text_addr;
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u32 text_len;
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u32 text_index;
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u32 *text;
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const u32 *text;
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/* Data section. */
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u32 data_addr;
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u32 data_len;
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u32 data_index;
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u32 *data;
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const u32 *data;
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/* SBSS section. */
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u32 sbss_addr;
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u32 sbss_len;
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u32 sbss_index;
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u32 *sbss;
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const u32 *sbss;
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/* BSS section. */
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u32 bss_addr;
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struct bce_softc
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{
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/* Interface info. Must be first!! */
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/* Interface info */
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struct ifnet *bce_ifp;
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/* Parent device handle */
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struct mtx bce_mtx;
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/* Interrupt handler. */
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driver_intr_t *bce_intr;
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void *bce_intrhand;
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int bce_irq_rid;
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int bce_msi_count;
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/* ASIC Chip ID. */
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u32 bce_chipid;
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u16 link_speed;
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/* Flash NVRAM settings */
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struct flash_spec *bce_flash_info;
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const struct flash_spec *bce_flash_info;
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/* Flash NVRAM size */
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u32 bce_flash_size;
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@ -6518,7 +6515,7 @@ struct bce_softc
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u32 bce_shmem_base;
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/* Name string */
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char *bce_name;
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const char *bce_name;
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/* Tracks the version of bootcode firmware. */
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char bce_bc_ver[32];
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};
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#endif /* __BCEREG_H_DEFINED */
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