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https://github.com/freebsd/freebsd-src
synced 2024-10-19 06:44:31 +00:00
Flesh out the TX power calibration for the AR9287.
I'm assuming for now that the AR9287 is only open-loop TX power control (as mine is) so I've hard-coded the attach path to fail if the NIC is not open-loop. This greatly simplifies the TX calibration path and the amount of code which needs to be ported over. This still isn't complete - the rate calculation code still needs to be ported and it all needs to be glued together. Obtained from: Linux ath9k
This commit is contained in:
Adrian Chadd
parent
141fa00b5f
commit
4551052dbe
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=222308
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@ -276,6 +276,17 @@ ar9287Attach(uint16_t devid, HAL_SOFTC sc,
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goto bad;
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}
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/*
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* We only implement open-loop TX power control
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* for the AR9287 in this codebase.
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*/
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if (! ath_hal_eepromGetFlag(ah, AR_EEP_OL_PWRCTRL)) {
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ath_hal_printf(ah, "[ath] AR9287 w/ closed-loop TX power control"
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" isn't supported.\n");
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ecode = HAL_ENOTSUPP;
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goto bad;
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}
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/*
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* Check whether the power table offset isn't the default.
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* This can occur with eeprom minor V21 or greater on Merlin.
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@ -30,6 +30,7 @@
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#include "ah_internal.h"
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#include "ah_eeprom_v14.h"
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#include "ah_eeprom_9287.h"
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#include "ar9002/ar9280.h"
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#include "ar5416/ar5416reg.h"
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@ -92,3 +93,74 @@ ar9287olcTemperatureCompensation(struct ath_hal *ah)
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AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, delta);
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}
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}
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void
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ar9287olcGetTxGainIndex(struct ath_hal *ah,
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const struct ieee80211_channel *chan,
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struct cal_data_op_loop_ar9287 *pRawDatasetOpLoop,
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uint8_t *pCalChans, uint16_t availPiers, int8_t *pPwr)
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{
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uint16_t idxL = 0, idxR = 0, numPiers;
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HAL_BOOL match;
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CHAN_CENTERS centers;
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ar5416GetChannelCenters(ah, chan, ¢ers);
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for (numPiers = 0; numPiers < availPiers; numPiers++) {
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if (pCalChans[numPiers] == AR5416_BCHAN_UNUSED)
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break;
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}
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match = ath_ee_getLowerUpperIndex(
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(uint8_t)FREQ2FBIN(centers.synth_center, IEEE80211_IS_CHAN_2GHZ(chan)),
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pCalChans, numPiers, &idxL, &idxR);
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if (match) {
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*pPwr = (int8_t) pRawDatasetOpLoop[idxL].pwrPdg[0][0];
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} else {
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*pPwr = ((int8_t) pRawDatasetOpLoop[idxL].pwrPdg[0][0] +
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(int8_t) pRawDatasetOpLoop[idxR].pwrPdg[0][0])/2;
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}
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}
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void
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ar9287olcSetPDADCs(struct ath_hal *ah, int32_t txPower,
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uint16_t chain)
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{
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uint32_t tmpVal;
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uint32_t a;
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/* Enable OLPC for chain 0 */
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tmpVal = OS_REG_READ(ah, 0xa270);
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tmpVal = tmpVal & 0xFCFFFFFF;
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tmpVal = tmpVal | (0x3 << 24);
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OS_REG_WRITE(ah, 0xa270, tmpVal);
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/* Enable OLPC for chain 1 */
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tmpVal = OS_REG_READ(ah, 0xb270);
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tmpVal = tmpVal & 0xFCFFFFFF;
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tmpVal = tmpVal | (0x3 << 24);
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OS_REG_WRITE(ah, 0xb270, tmpVal);
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/* Write the OLPC ref power for chain 0 */
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if (chain == 0) {
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tmpVal = OS_REG_READ(ah, 0xa398);
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tmpVal = tmpVal & 0xff00ffff;
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a = (txPower)&0xff;
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tmpVal = tmpVal | (a << 16);
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OS_REG_WRITE(ah, 0xa398, tmpVal);
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}
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/* Write the OLPC ref power for chain 1 */
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if (chain == 1) {
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tmpVal = OS_REG_READ(ah, 0xb398);
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tmpVal = tmpVal & 0xff00ffff;
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a = (txPower)&0xff;
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tmpVal = tmpVal | (a << 16);
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OS_REG_WRITE(ah, 0xb398, tmpVal);
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}
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}
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@ -21,5 +21,11 @@
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extern void ar9287olcInit(struct ath_hal *ah);
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extern void ar9287olcTemperatureCompensation(struct ath_hal *ah);
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extern void ar9287olcGetTxGainIndex(struct ath_hal *ah,
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const struct ieee80211_channel *chan,
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struct cal_data_op_loop_ar9287 *pRawDatasetOpLoop,
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uint8_t *pCalChans, uint16_t availPiers, int8_t *pPwr);
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extern void ar9287olcSetPDADCs(struct ath_hal *ah,
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int32_t txPower, uint16_t chain);
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#endif /* __AR9287_OLC_H__ */
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@ -33,13 +33,103 @@
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#include "ar9002/ar9287phy.h"
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#include "ar9002/ar9287an.h"
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#include "ar9002/ar9287_olc.h"
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#include "ar9002/ar9287_reset.h"
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/*
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* Set the TX power calibration table per-chain.
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*
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* This only supports open-loop TX power control for the AR9287.
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*/
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static void
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ar9287SetPowerCalTable(struct ath_hal *ah,
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const struct ieee80211_channel *chan, int16_t *pTxPowerIndexOffset)
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{
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struct cal_data_op_loop_ar9287 *pRawDatasetOpenLoop;
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uint8_t *pCalBChans = NULL;
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uint16_t pdGainOverlap_t2;
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uint16_t numPiers = 0, i;
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uint16_t numXpdGain, xpdMask;
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uint16_t xpdGainValues[AR5416_NUM_PD_GAINS] = {0, 0, 0, 0};
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uint32_t regChainOffset;
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HAL_EEPROM_9287 *ee = AH_PRIVATE(ah)->ah_eeprom;
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struct ar9287_eeprom *pEepData = &ee->ee_base;
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xpdMask = pEepData->modalHeader.xpdGain;
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if ((pEepData->baseEepHeader.version & AR9287_EEP_VER_MINOR_MASK) >=
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AR9287_EEP_MINOR_VER_2)
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pdGainOverlap_t2 = pEepData->modalHeader.pdGainOverlap;
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else
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pdGainOverlap_t2 = (uint16_t)(MS(OS_REG_READ(ah, AR_PHY_TPCRG5),
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AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
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/* Note: Kiwi should only be 2ghz.. */
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if (IEEE80211_IS_CHAN_2GHZ(chan)) {
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pCalBChans = pEepData->calFreqPier2G;
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numPiers = AR9287_NUM_2G_CAL_PIERS;
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pRawDatasetOpenLoop = (struct cal_data_op_loop_ar9287 *)pEepData->calPierData2G[0];
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AH5416(ah)->initPDADC = pRawDatasetOpenLoop->vpdPdg[0][0];
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}
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numXpdGain = 0;
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/* Calculate the value of xpdgains from the xpdGain Mask */
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for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
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if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
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if (numXpdGain >= AR5416_NUM_PD_GAINS)
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break;
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xpdGainValues[numXpdGain] =
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(uint16_t)(AR5416_PD_GAINS_IN_MASK-i);
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numXpdGain++;
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}
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}
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OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
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(numXpdGain - 1) & 0x3);
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OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
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xpdGainValues[0]);
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OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
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xpdGainValues[1]);
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OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3,
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xpdGainValues[2]);
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for (i = 0; i < AR9287_MAX_CHAINS; i++) {
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regChainOffset = i * 0x1000;
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if (pEepData->baseEepHeader.txMask & (1 << i)) {
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int8_t txPower;
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pRawDatasetOpenLoop =
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(struct cal_data_op_loop_ar9287 *)pEepData->calPierData2G[i];
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ar9287olcGetTxGainIndex(ah, chan,
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pRawDatasetOpenLoop,
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pCalBChans, numPiers,
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&txPower);
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ar9287olcSetPDADCs(ah, txPower, i);
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}
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}
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*pTxPowerIndexOffset = 0;
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}
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HAL_BOOL
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ar9287SetTransmitPower(struct ath_hal *ah,
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const struct ieee80211_channel *chan, uint16_t *rfXpdGain)
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{
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int16_t txPowerIndexOffset = 0;
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/* XXX TODO */
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/* Fetch per-rate power table for the given channel */
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/* Set open-loop TX power control calibration */
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ar9287SetPowerCalTable(ah, chan, &txPowerIndexOffset);
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/* Calculate regulatory maximum power level */
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/* Kiwi TX power starts at -5 dBm */
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/* Write TX power registers */
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return AH_TRUE;
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}
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