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Workaround for PCIe 4GB boundary issue

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Enforce a boundary of no more than 4GB - transfers crossing a 4GB
boundary can lead to data corruption due to PCIe limitations.  This
change is a less-intrusive workaround that can be quickly merged back
to older branches; a cleaner implementation will arrive in HEAD later
but may require KPI changes.

This change is based on a suggestion by jhb@.

Reviewed by:    scottl, jhb
Sponsored by:   Sandvine Incorporated
MFC after:      3 days
This commit is contained in:
Ed Maste 2012-02-28 19:42:40 +00:00
parent 95b1d16df5
commit 3f8e262e8c
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=232267
1 changed files with 8 additions and 0 deletions
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8
sys/x86/x86/busdma_machdep.c
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@ -227,6 +227,14 @@ bus_dma_tag_create(bus_dma_tag_t parent, bus_size_t alignment,
bus_dma_tag_t newtag;
int error = 0;
/* Always enforce at least a 4GB (2GB for PAE) boundary. */
#if defined(__amd64__)
if (boundary == 0 || boundary > ((bus_addr_t)1 << 32))
boundary = (bus_size_t)1 << 32;
#elif defined(PAE)
if (boundary == 0 || boundary > ((bus_addr_t)1 << 31))
boundary = (bus_size_t)1 << 31;
#endif
/* Basic sanity checking */
if (boundary != 0 && boundary < maxsegsz)
maxsegsz = boundary;