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[PowerPC64] Clear low-order bits of ARPN
PowerISA 2.07B says that the low-order p-12 bits of the real page number contained in ARPN and LP fields of a PTE must be 0s and are ignored by the hardware (Book III-S, 5.7.7.1), where 2^p is the actual page size in bytes, but we were clearing only the LP field. This worked on bare metal and QEMU with KVM, that ignore these bits, but caused a kernel panic on QEMU with TCG, that expects them to be cleared. This fixes running FreeBSD with HPT superpages enabled on QEMU with TCG. MFC after: 2 weeks Sponsored by: Eldorado Research Institute (eldorado.org.br)
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@ -3717,7 +3717,7 @@ moea64_sp_enter(pmap_t pmap, vm_offset_t va, vm_page_t m,
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pvo = pvos[i];
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pvo->pvo_pte.prot = prot;
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pvo->pvo_pte.pa = (pa & ~LPTE_LP_MASK) | LPTE_LP_4K_16M |
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pvo->pvo_pte.pa = (pa & ~HPT_SP_MASK) | LPTE_LP_4K_16M |
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moea64_calc_wimg(pa, pmap_page_get_memattr(m));
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if ((flags & PMAP_ENTER_WIRED) != 0)
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@ -3874,7 +3874,7 @@ moea64_sp_promote(pmap_t pmap, vm_offset_t va, vm_page_t m)
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for (pvo = first, va_end = PVO_VADDR(pvo) + HPT_SP_SIZE;
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pvo != NULL && PVO_VADDR(pvo) < va_end;
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pvo = RB_NEXT(pvo_tree, &pmap->pmap_pvo, pvo)) {
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pvo->pvo_pte.pa &= ~LPTE_LP_MASK;
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pvo->pvo_pte.pa &= ADDR_POFF | ~HPT_SP_MASK;
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pvo->pvo_pte.pa |= LPTE_LP_4K_16M;
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pvo->pvo_vaddr |= PVO_LARGE;
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}
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