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dwc: Move the dma reset code in dwc1000_dma.c

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No functional changes intended
This commit is contained in:
Emmanuel Vadot 2023-10-04 07:55:11 +02:00
parent f0a7dd7703
commit 363b7c39fb
4 changed files with 30 additions and 17 deletions
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1
sys/dev/dwc/dwc1000_core.h
View file

@ -34,6 +34,7 @@ int dwc1000_miibus_read_reg(device_t dev, int phy, int reg);
int dwc1000_miibus_write_reg(device_t dev, int phy, int reg, int val);
void dwc1000_miibus_statchg(device_t dev);
void dwc1000_core_setup(struct dwc_softc *sc);
int dwc1000_core_reset(struct dwc_softc *sc);
void dwc1000_enable_mac(struct dwc_softc *sc, bool enable);
void dwc1000_enable_csum_offload(struct dwc_softc *sc);
void dwc1000_setup_rxfilter(struct dwc_softc *sc);

24
sys/dev/dwc/dwc1000_dma.c
View file

@ -61,7 +61,7 @@
#include <dev/dwc/dwc1000_dma.h>
#define WATCHDOG_TIMEOUT_SECS 5
#define DMA_RESET_TIMEOUT 100
/* TX descriptors - TDESC0 is almost unified */
#define TDESC0_OWN (1U << 31)
@ -598,6 +598,28 @@ dma1000_stop(struct dwc_softc *sc)
WRITE4(sc, OPERATION_MODE, reg);
}
int
dma1000_reset(struct dwc_softc *sc)
{
uint32_t reg;
int i;
reg = READ4(sc, BUS_MODE);
reg |= (BUS_MODE_SWR);
WRITE4(sc, BUS_MODE, reg);
for (i = 0; i < DMA_RESET_TIMEOUT; i++) {
if ((READ4(sc, BUS_MODE) & BUS_MODE_SWR) == 0)
break;
DELAY(10);
}
if (i >= DMA_RESET_TIMEOUT) {
return (ENXIO);
}
return (0);
}
/*
* Create the bus_dma resources
*/

1
sys/dev/dwc/dwc1000_dma.h
View file

@ -46,6 +46,7 @@ int dma1000_init(struct dwc_softc *sc);
void dma1000_free(struct dwc_softc *sc);
void dma1000_start(struct dwc_softc *sc);
void dma1000_stop(struct dwc_softc *sc);
int dma1000_reset(struct dwc_softc *sc);
int dma1000_setup_txbuf(struct dwc_softc *sc, int idx, struct mbuf **mp);
void dma1000_txfinish_locked(struct dwc_softc *sc);
void dma1000_rxfinish_locked(struct dwc_softc *sc);

21
sys/dev/dwc/if_dwc.c
View file

@ -78,8 +78,6 @@
#include "gpio_if.h"
#include "miibus_if.h"
#define MAC_RESET_TIMEOUT 100
static struct resource_spec dwc_spec[] = {
{ SYS_RES_MEMORY, 0, RF_ACTIVE },
{ SYS_RES_IRQ, 0, RF_ACTIVE },
@ -499,7 +497,7 @@ dwc_attach(device_t dev)
uint8_t macaddr[ETHER_ADDR_LEN];
struct dwc_softc *sc;
if_t ifp;
int error, i;
int error;
uint32_t reg;
uint32_t txpbl, rxpbl, pbl;
bool nopblx8 = false;
@ -581,19 +579,10 @@ dwc_attach(device_t dev)
}
/* Reset */
reg = READ4(sc, BUS_MODE);
reg |= (BUS_MODE_SWR);
WRITE4(sc, BUS_MODE, reg);
for (i = 0; i < MAC_RESET_TIMEOUT; i++) {
if ((READ4(sc, BUS_MODE) & BUS_MODE_SWR) == 0)
break;
DELAY(10);
}
if (i >= MAC_RESET_TIMEOUT) {
device_printf(sc->dev, "Can't reset DWC.\n");
bus_release_resources(dev, dwc_spec, sc->res);
return (ENXIO);
if ((error = dma1000_reset(sc)) != 0) {
device_printf(sc->dev, "Can't reset DMA controller.\n");
bus_release_resources(sc->dev, dwc_spec, sc->res);
return (error);
}
reg = BUS_MODE_USP;