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Fix a bug where we would think that the L1 instruction and data cache are

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present even though the line size field in the CP0 Config1 register is 0.

Approved by: imp (mentor)
This commit is contained in:
Neel Natu 2009-10-20 04:36:08 +00:00
parent d428afbbbb
commit 344214e344
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/projects/mips/; revision=198264
1 changed files with 4 additions and 4 deletions
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8
sys/mips/mips/cpu.c
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@ -94,9 +94,9 @@ mips_get_identity(struct mips_cpuinfo *cpuinfo)
((cfg1 & MIPS_CONFIG1_TLBSZ_MASK) >> MIPS_CONFIG1_TLBSZ_SHIFT) + 1;
/* L1 instruction cache. */
tmp = 1 << (((cfg1 & MIPS_CONFIG1_IL_MASK) >> MIPS_CONFIG1_IL_SHIFT) + 1);
tmp = (cfg1 & MIPS_CONFIG1_IL_MASK) >> MIPS_CONFIG1_IL_SHIFT;
if (tmp != 0) {
cpuinfo->l1.ic_linesize = tmp;
cpuinfo->l1.ic_linesize = 1 << (tmp + 1);
cpuinfo->l1.ic_nways = (((cfg1 & MIPS_CONFIG1_IA_MASK) >> MIPS_CONFIG1_IA_SHIFT)) + 1;
cpuinfo->l1.ic_nsets =
1 << (((cfg1 & MIPS_CONFIG1_IS_MASK) >> MIPS_CONFIG1_IS_SHIFT) + 6);
@ -105,9 +105,9 @@ mips_get_identity(struct mips_cpuinfo *cpuinfo)
}
/* L1 data cache. */
tmp = 1 << (((cfg1 & MIPS_CONFIG1_DL_MASK) >> MIPS_CONFIG1_DL_SHIFT) + 1);
tmp = (cfg1 & MIPS_CONFIG1_DL_MASK) >> MIPS_CONFIG1_DL_SHIFT;
if (tmp != 0) {
cpuinfo->l1.dc_linesize = tmp;
cpuinfo->l1.dc_linesize = 1 << (tmp + 1);
cpuinfo->l1.dc_nways =
(((cfg1 & MIPS_CONFIG1_DA_MASK) >> MIPS_CONFIG1_DA_SHIFT)) + 1;
cpuinfo->l1.dc_nsets =