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pcireg.h: Add AMD IOMMU Base Cap definitions

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Reviewed by:	emaste
Sponsored by:	Advanced Micro Devices (AMD)
Sponsored by:	The FreeBSD Foundation
MFC after:	1 week
Differential revision:	https://reviews.freebsd.org/D44732
This commit is contained in:
Konstantin Belousov 2024-04-07 04:25:46 +03:00
parent 1cd9868f04
commit 33adb388c7
1 changed files with 52 additions and 0 deletions
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52
sys/dev/pci/pcireg.h
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@ -1125,4 +1125,56 @@
#define PCIM_ACS_UNCLAIMED_REQ_REDIRECT_CTL 0x1000
#define PCIR_ACS_EGRESS_CONTROL_VECTOR 0x8
/*
* AMD IOMMU Base Capability
* From AMD I/O Virtualization Technology (IOMMU) Specification
* Publication # 48882 Revision: 3.09-PUB Date: October 2023
*/
#define PCIR_AMDIOMMU_CAP_HEADER 0x0000
#define PCIR_AMDIOMMU_BASE_LOW 0x0004
#define PCIR_AMDIOMMU_BASE_HIGH 0x0008
#define PCIR_AMDIOMMU_RANGE 0x000c
#define PCIR_AMDIOMMU_MISC0 0x0010
#define PCIR_AMDIOMMU_MISC1 0x0014
#define PCIM_AMDIOMMU_CAP_CAPEXT (1 << 28)
#define PCIM_AMDIOMMU_CAP_EFR (1 << 27)
#define PCIM_AMDIOMMU_CAP_NPCACHE (1 << 26)
#define PCIM_AMDIOMMU_CAP_HTTUN (1 << 25)
#define PCIM_AMDIOMMU_CAP_IOTLB (1 << 24)
#define PCIM_AMDIOMMU_CAP_REV_MASK (0x1f << 19)
#define PCIM_AMDIOMMU_CAP_REV_VAL (0x1 << 19)
#define PCIM_AMDIOMMU_CAP_TYPE_MASK (7 << 16)
#define PCIM_AMDIOMMU_CAP_TYPE_VAL (0x3 << 16)
#define PCIM_AMDIOMMU_BASE_LOW_EN 0x00000001
#define PCIM_AMDIOMMU_BASE_LOW_ADDRM 0xffffc000
#define PCIM_AMDIOMMU_RANGE_UNITID_MASK 0x1f
#define PCIM_AMDIOMMU_RANGE_RNGVALID (1 << 7)
#define PCIM_AMDIOMMU_RANGE_BUSNUM_MASK (0xffffu << 8)
#define PCIM_AMDIOMMU_RANGE_FIRSTDEV_MASK (0xffffu << 16)
#define PCIM_AMDIOMMU_RANGE_LASTDEV_MASK (0xffffu << 24)
#define PCIM_AMDIOMMU_MISC0_MSINUMPPR_MASK (0x1f << 27)
#define PCIM_AMDIOMMU_MISC0_HTATSRESV (1 << 22)
#define PCIM_AMDIOMMU_MISC0_VASIZE_MASK (0x7f << 15)
#define PCIM_AMDIOMMU_MISC0_PASIZE_MASK (0x7f << 8)
#define PCIM_AMDIOMMU_MISC0_GVASIZE_MASK (0x3 << 5)
#define PCIM_AMDIOMMU_MISC0_MSINUM_MASK 0x1f
#define PCIM_AMDIOMMU_MISC0_VASIZE_32 (0x20 << 15)
#define PCIM_AMDIOMMU_MISC0_VASIZE_40 (0x28 << 15)
#define PCIM_AMDIOMMU_MISC0_VASIZE_48 (0x30 << 15)
#define PCIM_AMDIOMMU_MISC0_VASIZE_64 (0x40 << 15)
#define PCIM_AMDIOMMU_MISC0_PASIZE_40 (0x28 << 8)
#define PCIM_AMDIOMMU_MISC0_PASIZE_48 (0x30 << 8)
#define PCIM_AMDIOMMU_MISC0_PASIZE_52 (0x34 << 8)
#define PCIM_AMDIOMMU_MISC0_GVASIZE_48 (0x2 << 5)
#define PCIM_AMDIOMMU_MISC0_GVASIZE_57 (0x3 << 5)
#define PCIM_AMDIOMMU_MISC1_MSINUMGA_MASK 0x1f
#endif /* __PCI_PCIREG_H */