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Invalidate TLB at boot using the correct IS settings on newer-than-POWER5

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CPUs.

MFC after:	3 weeks
This commit is contained in:
Nathan Whitehorn 2017-11-25 22:10:10 +00:00
parent d225a2a9c9
commit 312fb3d8dd
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=326211
1 changed files with 16 additions and 2 deletions
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18
sys/powerpc/aim/moea64_native.c
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@ -382,7 +382,7 @@ moea64_cpu_bootstrap_native(mmu_t mmup, int ap)
__asm __volatile ("slbmfee %0,%1; slbie %0;" : "=r"(seg0) :
"r"(0));
for (i = 0; i < 64; i++) {
for (i = 0; i < n_slbs; i++) {
if (!(slb[i].slbe & SLBE_VALID))
continue;
@ -465,9 +465,23 @@ tlbia(void)
register_t msr, scratch;
#endif
i = 0xc00; /* IS = 11 */
switch (mfpvr() >> 16) {
case IBM970:
case IBM970FX:
case IBM970MP:
case IBM970GX:
case IBMPOWER4:
case IBMPOWER4PLUS:
case IBMPOWER5:
case IBMPOWER5PLUS:
i = 0; /* IS not supported */
break;
}
TLBSYNC();
for (i = 0; i < 0xFF000; i += 0x00001000) {
for (; i < 0x200000; i += 0x00001000) {
#ifdef __powerpc64__
__asm __volatile("tlbiel %0" :: "r"(i));
#else