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Add a Saved Process Status Register bit for AArch32 execution mode.

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The documentation on the Saved Process Status Register (SPSR) is a bit
weird; the M[4] bit is documented separately from M[3:0]. The M[4] bit
can be toggled to switch to 32-bit execution mode. This functionality is
orthogonal to M[3:0].

Change the definition of PSR_M_MASK to no longer include M[4]. Add a new
definition, PSR_AARCH32 that can be used to toggle 32-bit independently.
This bit will be used by the cloudabi32 code to force execution of
userspace code in 32-bit mode.

Reviewed by:	andrew
Differential Revision:	https://reviews.freebsd.org/D13148
This commit is contained in:
Ed Schouten 2017-11-26 14:56:23 +00:00
parent 2d19a20d5d
commit 2b6a8dd52c
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=326230
2 changed files with 3 additions and 3 deletions
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2
sys/arm64/arm64/machdep.c
View file

@ -405,7 +405,7 @@ set_mcontext(struct thread *td, mcontext_t *mcp)
spsr = mcp->mc_gpregs.gp_spsr;
if ((spsr & PSR_M_MASK) != PSR_M_EL0t ||
(spsr & (PSR_F | PSR_I | PSR_A | PSR_D)) != 0)
(spsr & (PSR_AARCH32 | PSR_F | PSR_I | PSR_A | PSR_D)) != 0)
return (EINVAL);
memcpy(tf->tf_x, mcp->mc_gpregs.gp_x, sizeof(tf->tf_x));

4
sys/arm64/include/armreg.h
View file

@ -549,7 +549,6 @@
/* SPSR_EL1 */
/*
* When the exception is taken in AArch64:
* M[4] is 0 for AArch64 mode
* M[3:2] is the exception level
* M[1] is unused
* M[0] is the SP select:
@ -561,8 +560,9 @@
#define PSR_M_EL1h 0x00000005
#define PSR_M_EL2t 0x00000008
#define PSR_M_EL2h 0x00000009
#define PSR_M_MASK 0x0000001f
#define PSR_M_MASK 0x0000000f
#define PSR_AARCH32 0x00000010
#define PSR_F 0x00000040
#define PSR_I 0x00000080
#define PSR_A 0x00000100