diff --git a/sys/dev/gem/if_gem.c b/sys/dev/gem/if_gem.c index ced67eea1230..f92915119be3 100644 --- a/sys/dev/gem/if_gem.c +++ b/sys/dev/gem/if_gem.c @@ -1,6 +1,7 @@ /*- * Copyright (C) 2001 Eduardo Horvath. * Copyright (c) 2001-2003 Thomas Moestl + * Copyright (c) 2007 Marius Strobl * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -83,53 +84,53 @@ __FBSDID("$FreeBSD$"); CTASSERT(powerof2(GEM_NRXDESC) && GEM_NRXDESC >= 32 && GEM_NRXDESC <= 8192); CTASSERT(powerof2(GEM_NTXDESC) && GEM_NTXDESC >= 32 && GEM_NTXDESC <= 8192); -#define TRIES 10000 +#define TRIES 10000 /* - * The GEM hardware support basic TCP/UDP checksum offloading. However, + * The GEM hardware support basic TCP/UDP checksum offloading. However, * the hardware doesn't compensate the checksum for UDP datagram which - * can yield to 0x0. As a safe guard, UDP checksum offload is disabled - * by default. It can be reactivated by setting special link option + * can yield to 0x0. As a safe guard, UDP checksum offload is disabled + * by default. It can be reactivated by setting special link option * link0 with ifconfig(8). */ #define GEM_CSUM_FEATURES (CSUM_TCP) -static void gem_start(struct ifnet *); -static void gem_start_locked(struct ifnet *); -static void gem_stop(struct ifnet *, int); -static int gem_ioctl(struct ifnet *, u_long, caddr_t); -static void gem_cddma_callback(void *, bus_dma_segment_t *, int, int); -static __inline void gem_txcksum(struct gem_softc *, struct mbuf *, uint64_t *); -static __inline void gem_rxcksum(struct mbuf *, uint64_t); -static void gem_tick(void *); -static int gem_watchdog(struct gem_softc *); -static void gem_init(void *); -static void gem_init_locked(struct gem_softc *); -static void gem_init_regs(struct gem_softc *); -static u_int gem_ringsize(u_int); -static int gem_meminit(struct gem_softc *); -static struct mbuf *gem_defrag(struct mbuf *, int, int); -static int gem_load_txmbuf(struct gem_softc *, struct mbuf **); -static void gem_mifinit(struct gem_softc *); -static int gem_bitwait(struct gem_softc *, bus_addr_t, u_int32_t, - u_int32_t); -static void gem_reset(struct gem_softc *); -static int gem_reset_rx(struct gem_softc *); +static int gem_add_rxbuf(struct gem_softc *sc, int idx); +static int gem_bitwait(struct gem_softc *sc, bus_addr_t r, uint32_t clr, + uint32_t set); +static void gem_cddma_callback(void *xsc, bus_dma_segment_t *segs, + int nsegs, int error); +static struct mbuf *gem_defrag(struct mbuf *m0, int how, int maxfrags); +static int gem_disable_rx(struct gem_softc *sc); +static int gem_disable_tx(struct gem_softc *sc); +static void gem_eint(struct gem_softc *sc, u_int status); +static void gem_init(void *xsc); +static void gem_init_locked(struct gem_softc *sc); +static void gem_init_regs(struct gem_softc *sc); +static int gem_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data); +static int gem_load_txmbuf(struct gem_softc *sc, struct mbuf **m_head); +static int gem_meminit(struct gem_softc *sc); +static void gem_mifinit(struct gem_softc *sc); +static void gem_reset(struct gem_softc *sc); +static int gem_reset_rx(struct gem_softc *sc); static void gem_reset_rxdma(struct gem_softc *sc); -static int gem_reset_tx(struct gem_softc *); -static int gem_disable_rx(struct gem_softc *); -static int gem_disable_tx(struct gem_softc *); -static void gem_rxdrain(struct gem_softc *); -static int gem_add_rxbuf(struct gem_softc *, int); -static void gem_setladrf(struct gem_softc *); - -struct mbuf *gem_get(struct gem_softc *, int, int); -static void gem_eint(struct gem_softc *, u_int); -static void gem_rint(struct gem_softc *); +static int gem_reset_tx(struct gem_softc *sc); +static u_int gem_ringsize(u_int sz); +static void gem_rint(struct gem_softc *sc); #ifdef GEM_RINT_TIMEOUT -static void gem_rint_timeout(void *); +static void gem_rint_timeout(void *arg); #endif -static void gem_tint(struct gem_softc *); +static __inline void gem_rxcksum(struct mbuf *m, uint64_t flags); +static void gem_rxdrain(struct gem_softc *sc); +static void gem_setladrf(struct gem_softc *sc); +static void gem_start(struct ifnet *ifp); +static void gem_start_locked(struct ifnet *ifp); +static void gem_stop(struct ifnet *ifp, int disable); +static void gem_tick(void *arg); +static void gem_tint(struct gem_softc *sc); +static __inline void gem_txcksum(struct gem_softc *sc, struct mbuf *m, + uint64_t *cflags); +static int gem_watchdog(struct gem_softc *sc); devclass_t gem_devclass; DRIVER_MODULE(miibus, gem, miibus_driver, miibus_devclass, 0, 0); @@ -140,20 +141,13 @@ MODULE_DEPEND(gem, miibus, 1, 1, 1); #define KTR_GEM KTR_CT2 #endif -#define GEM_NSEGS GEM_NTXDESC - -/* - * gem_attach: - * - * Attach a Gem interface to the system. - */ int -gem_attach(sc) - struct gem_softc *sc; +gem_attach(struct gem_softc *sc) { + struct gem_txsoft *txs; struct ifnet *ifp; - int i, error; - u_int32_t v; + int error, i; + uint32_t v; ifp = sc->sc_ifp = if_alloc(IFT_ETHER); if (ifp == NULL) @@ -170,8 +164,8 @@ gem_attach(sc) error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, - BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, - &sc->sc_pdmatag); + BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, + NULL, &sc->sc_pdmatag); if (error) goto fail_ifnet; @@ -197,15 +191,15 @@ gem_attach(sc) goto fail_ttag; /* - * Allocate the control data structures, and create and load the + * Allocate the control data structures, create and load the * DMA map for it. */ if ((error = bus_dmamem_alloc(sc->sc_cdmatag, (void **)&sc->sc_control_data, BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->sc_cddmamap))) { - device_printf(sc->sc_dev, "unable to allocate control data," - " error = %d\n", error); + device_printf(sc->sc_dev, + "unable to allocate control data, error = %d\n", error); goto fail_ctag; } @@ -213,8 +207,9 @@ gem_attach(sc) if ((error = bus_dmamap_load(sc->sc_cdmatag, sc->sc_cddmamap, sc->sc_control_data, sizeof(struct gem_control_data), gem_cddma_callback, sc, 0)) != 0 || sc->sc_cddma == 0) { - device_printf(sc->sc_dev, "unable to load control data DMA " - "map, error = %d\n", error); + device_printf(sc->sc_dev, + "unable to load control data DMA map, error = %d\n", + error); goto fail_cmem; } @@ -229,15 +224,14 @@ gem_attach(sc) */ error = ENOMEM; for (i = 0; i < GEM_TXQUEUELEN; i++) { - struct gem_txsoft *txs; - txs = &sc->sc_txsoft[i]; txs->txs_mbuf = NULL; txs->txs_ndescs = 0; if ((error = bus_dmamap_create(sc->sc_tdmatag, 0, &txs->txs_dmamap)) != 0) { - device_printf(sc->sc_dev, "unable to create tx DMA map " - "%d, error = %d\n", i, error); + device_printf(sc->sc_dev, + "unable to create TX DMA map %d, error = %d\n", + i, error); goto fail_txd; } STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); @@ -249,8 +243,9 @@ gem_attach(sc) for (i = 0; i < GEM_NRXDESC; i++) { if ((error = bus_dmamap_create(sc->sc_rdmatag, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { - device_printf(sc->sc_dev, "unable to create rx DMA map " - "%d, error = %d\n", i, error); + device_printf(sc->sc_dev, + "unable to create RX DMA map %d, error = %d\n", + i, error); goto fail_rxd; } sc->sc_rxsoft[i].rxs_mbuf = NULL; @@ -372,38 +367,35 @@ gem_attach(sc) * Free any resources we've allocated during the failed attach * attempt. Do this in reverse order and fall through. */ -fail_rxd: - for (i = 0; i < GEM_NRXDESC; i++) { + fail_rxd: + for (i = 0; i < GEM_NRXDESC; i++) if (sc->sc_rxsoft[i].rxs_dmamap != NULL) bus_dmamap_destroy(sc->sc_rdmatag, sc->sc_rxsoft[i].rxs_dmamap); - } -fail_txd: - for (i = 0; i < GEM_TXQUEUELEN; i++) { + fail_txd: + for (i = 0; i < GEM_TXQUEUELEN; i++) if (sc->sc_txsoft[i].txs_dmamap != NULL) bus_dmamap_destroy(sc->sc_tdmatag, sc->sc_txsoft[i].txs_dmamap); - } bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap); -fail_cmem: + fail_cmem: bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data, sc->sc_cddmamap); -fail_ctag: + fail_ctag: bus_dma_tag_destroy(sc->sc_cdmatag); -fail_ttag: + fail_ttag: bus_dma_tag_destroy(sc->sc_tdmatag); -fail_rtag: + fail_rtag: bus_dma_tag_destroy(sc->sc_rdmatag); -fail_ptag: + fail_ptag: bus_dma_tag_destroy(sc->sc_pdmatag); -fail_ifnet: + fail_ifnet: if_free(ifp); return (error); } void -gem_detach(sc) - struct gem_softc *sc; +gem_detach(struct gem_softc *sc) { struct ifnet *ifp = sc->sc_ifp; int i; @@ -419,16 +411,14 @@ gem_detach(sc) if_free(ifp); device_delete_child(sc->sc_dev, sc->sc_miibus); - for (i = 0; i < GEM_NRXDESC; i++) { + for (i = 0; i < GEM_NRXDESC; i++) if (sc->sc_rxsoft[i].rxs_dmamap != NULL) bus_dmamap_destroy(sc->sc_rdmatag, sc->sc_rxsoft[i].rxs_dmamap); - } - for (i = 0; i < GEM_TXQUEUELEN; i++) { + for (i = 0; i < GEM_TXQUEUELEN; i++) if (sc->sc_txsoft[i].txs_dmamap != NULL) bus_dmamap_destroy(sc->sc_tdmatag, sc->sc_txsoft[i].txs_dmamap); - } GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD); GEM_CDSYNC(sc, BUS_DMASYNC_POSTWRITE); bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap); @@ -441,8 +431,7 @@ gem_detach(sc) } void -gem_suspend(sc) - struct gem_softc *sc; +gem_suspend(struct gem_softc *sc) { struct ifnet *ifp = sc->sc_ifp; @@ -452,8 +441,7 @@ gem_suspend(sc) } void -gem_resume(sc) - struct gem_softc *sc; +gem_resume(struct gem_softc *sc) { struct ifnet *ifp = sc->sc_ifp; @@ -471,10 +459,10 @@ gem_resume(sc) static __inline void gem_txcksum(struct gem_softc *sc, struct mbuf *m, uint64_t *cflags) { - struct mbuf *m0; - struct ip *ip; - uint64_t offset, offset2; char *p; + struct ip *ip; + struct mbuf *m0; + uint64_t offset, offset2; m0 = m; offset = sizeof(struct ip) + ETHER_HDR_LEN; @@ -483,7 +471,7 @@ gem_txcksum(struct gem_softc *sc, struct mbuf *m, uint64_t *cflags) if (m == NULL || m->m_len < ETHER_HDR_LEN) { device_printf(sc->sc_dev, "%s: m_len < ETHER_HDR_LEN\n", __func__); - /* checksum will be corrupted */ + /* Checksum will be corrupted. */ m = m0; goto sendit; } @@ -491,14 +479,14 @@ gem_txcksum(struct gem_softc *sc, struct mbuf *m, uint64_t *cflags) if (m->m_len != ETHER_HDR_LEN) { device_printf(sc->sc_dev, "%s: m_len != ETHER_HDR_LEN\n", __func__); - /* checksum will be corrupted */ + /* Checksum will be corrupted. */ m = m0; goto sendit; } for(m = m->m_next; m && m->m_len == 0; m = m->m_next) ; if (m == NULL) { - /* checksum will be corrupted */ + /* Checksum will be corrupted. */ m = m0; goto sendit; } @@ -510,7 +498,7 @@ gem_txcksum(struct gem_softc *sc, struct mbuf *m, uint64_t *cflags) } offset = (ip->ip_hl << 2) + ETHER_HDR_LEN; -sendit: + sendit: offset2 = m->m_pkthdr.csum_data; *cflags = offset << GEM_TD_CXSUM_STARTSHFT; *cflags |= ((offset + offset2) << GEM_TD_CXSUM_STUFFSHFT); @@ -523,9 +511,10 @@ gem_rxcksum(struct mbuf *m, uint64_t flags) struct ether_header *eh; struct ip *ip; struct udphdr *uh; + uint16_t *opts; int32_t hlen, len, pktlen; - uint16_t cksum, *opts; uint32_t temp32; + uint16_t cksum; pktlen = m->m_pkthdr.len; if (pktlen < sizeof(struct ether_header) + sizeof(struct ip)) @@ -546,7 +535,7 @@ gem_rxcksum(struct mbuf *m, uint64_t flags) if (ntohs(ip->ip_len) != pktlen) return; if (ip->ip_off & htons(IP_MF | IP_OFFMASK)) - return; /* can't handle fragmented packet */ + return; /* Cannot handle fragmented packet. */ switch (ip->ip_p) { case IPPROTO_TCP: @@ -580,26 +569,19 @@ gem_rxcksum(struct mbuf *m, uint64_t flags) } static void -gem_cddma_callback(xsc, segs, nsegs, error) - void *xsc; - bus_dma_segment_t *segs; - int nsegs; - int error; +gem_cddma_callback(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) { - struct gem_softc *sc = (struct gem_softc *)xsc; + struct gem_softc *sc = xsc; if (error != 0) return; - if (nsegs != 1) { - /* can't happen... */ + if (nsegs != 1) panic("%s: bad control buffer segment count", __func__); - } sc->sc_cddma = segs[0].ds_addr; } static void -gem_tick(arg) - void *arg; +gem_tick(void *arg) { struct gem_softc *sc = arg; struct ifnet *ifp; @@ -608,7 +590,7 @@ gem_tick(arg) ifp = sc->sc_ifp; /* - * Unload collision counters + * Unload collision counters. */ ifp->if_collisions += bus_read_4(sc->sc_res[0], GEM_MAC_NORM_COLL_CNT) + @@ -633,14 +615,10 @@ gem_tick(arg) } static int -gem_bitwait(sc, r, clr, set) - struct gem_softc *sc; - bus_addr_t r; - u_int32_t clr; - u_int32_t set; +gem_bitwait(struct gem_softc *sc, bus_addr_t r, uint32_t clr, uint32_t set) { int i; - u_int32_t reg; + uint32_t reg; for (i = TRIES; i--; DELAY(100)) { reg = bus_read_4(sc->sc_res[0], r); @@ -661,21 +639,15 @@ gem_reset(sc) gem_reset_rx(sc); gem_reset_tx(sc); - /* Do a full reset */ + /* Do a full reset. */ bus_write_4(sc->sc_res[0], GEM_RESET, GEM_RESET_RX | GEM_RESET_TX); bus_barrier(sc->sc_res[0], GEM_RESET, 4, BUS_SPACE_BARRIER_WRITE); if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0)) device_printf(sc->sc_dev, "cannot reset device\n"); } -/* - * gem_rxdrain: - * - * Drain the receive queue. - */ static void -gem_rxdrain(sc) - struct gem_softc *sc; +gem_rxdrain(struct gem_softc *sc) { struct gem_rxsoft *rxs; int i; @@ -692,15 +664,10 @@ gem_rxdrain(sc) } } -/* - * Reset the whole thing. - */ static void -gem_stop(ifp, disable) - struct ifnet *ifp; - int disable; +gem_stop(struct ifnet *ifp, int disable) { - struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; + struct gem_softc *sc = ifp->if_softc; struct gem_txsoft *txs; #ifdef GEM_DEBUG @@ -712,7 +679,7 @@ gem_stop(ifp, disable) callout_stop(&sc->sc_rx_ch); #endif - /* XXX - Should we reset these instead? */ + /* XXX should we reset these instead? */ gem_disable_tx(sc); gem_disable_rx(sc); @@ -744,12 +711,8 @@ gem_stop(ifp, disable) sc->sc_wdog_timer = 0; } -/* - * Reset the receiver - */ static int -gem_reset_rx(sc) - struct gem_softc *sc; +gem_reset_rx(struct gem_softc *sc) { /* @@ -798,7 +761,7 @@ gem_reset_rxdma(struct gem_softc *sc) bus_write_4(sc->sc_res[0], GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); bus_write_4(sc->sc_res[0], GEM_RX_KICK, GEM_NRXDESC - 4); bus_write_4(sc->sc_res[0], GEM_RX_CONFIG, - gem_ringsize(GEM_NRXDESC /*XXX*/) | + gem_ringsize(GEM_NRXDESC /* XXX */) | ((ETHER_HDR_LEN + sizeof(struct ip)) << GEM_RX_CONFIG_CXM_START_SHFT) | (GEM_THRSH_1024 << GEM_RX_CONFIG_FIFO_THRS_SHIFT) | @@ -806,21 +769,20 @@ gem_reset_rxdma(struct gem_softc *sc) bus_write_4(sc->sc_res[0], GEM_RX_BLANKING, (6 << GEM_RX_BLANKING_TIME_SHIFT) | 6); bus_write_4(sc->sc_res[0], GEM_RX_PAUSE_THRESH, - (3 * sc->sc_rxfifosize / 256) | ((sc->sc_rxfifosize / 256) << 12)); + (3 * sc->sc_rxfifosize / 256) | + ((sc->sc_rxfifosize / 256) << 12)); bus_write_4(sc->sc_res[0], GEM_RX_CONFIG, - bus_read_4(sc->sc_res[0], GEM_RX_CONFIG) | GEM_RX_CONFIG_RXDMA_EN); + bus_read_4(sc->sc_res[0], GEM_RX_CONFIG) | + GEM_RX_CONFIG_RXDMA_EN); bus_write_4(sc->sc_res[0], GEM_MAC_RX_MASK, GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT); bus_write_4(sc->sc_res[0], GEM_MAC_RX_CONFIG, - bus_read_4(sc->sc_res[0], GEM_MAC_RX_CONFIG) | GEM_MAC_RX_ENABLE); + bus_read_4(sc->sc_res[0], GEM_MAC_RX_CONFIG) | + GEM_MAC_RX_ENABLE); } -/* - * Reset the transmitter - */ static int -gem_reset_tx(sc) - struct gem_softc *sc; +gem_reset_tx(struct gem_softc *sc) { /* @@ -843,21 +805,16 @@ gem_reset_tx(sc) return (0); } -/* - * disable receiver. - */ static int -gem_disable_rx(sc) - struct gem_softc *sc; +gem_disable_rx(struct gem_softc *sc) { - u_int32_t cfg; + uint32_t cfg; - /* Flip the enable bit */ cfg = bus_read_4(sc->sc_res[0], GEM_MAC_RX_CONFIG); cfg &= ~GEM_MAC_RX_ENABLE; bus_write_4(sc->sc_res[0], GEM_MAC_RX_CONFIG, cfg); bus_barrier(sc->sc_res[0], GEM_MAC_RX_CONFIG, 4, - BUS_SPACE_BARRIER_WRITE); + BUS_SPACE_BARRIER_WRITE); return (gem_bitwait(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)); } @@ -865,12 +822,10 @@ gem_disable_rx(sc) * disable transmitter. */ static int -gem_disable_tx(sc) - struct gem_softc *sc; +gem_disable_tx(struct gem_softc *sc) { - u_int32_t cfg; + uint32_t cfg; - /* Flip the enable bit */ cfg = bus_read_4(sc->sc_res[0], GEM_MAC_TX_CONFIG); cfg &= ~GEM_MAC_TX_ENABLE; bus_write_4(sc->sc_res[0], GEM_MAC_TX_CONFIG, cfg); @@ -879,15 +834,12 @@ gem_disable_tx(sc) return (gem_bitwait(sc, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)); } -/* - * Initialize interface. - */ static int gem_meminit(sc) struct gem_softc *sc; { struct gem_rxsoft *rxs; - int i, error; + int error, i; /* * Initialize the transmit descriptor ring. @@ -908,12 +860,12 @@ gem_meminit(sc) rxs = &sc->sc_rxsoft[i]; if (rxs->rxs_mbuf == NULL) { if ((error = gem_add_rxbuf(sc, i)) != 0) { - device_printf(sc->sc_dev, "unable to " - "allocate or map rx buffer %d, error = " - "%d\n", i, error); + device_printf(sc->sc_dev, + "unable to allocate or map RX buffer %d, " + "error = %d\n", i, error); /* - * XXX Should attempt to run with fewer receive - * XXX buffers instead of just failing. + * XXX we should attempt to run with fewer + * receive buffers instead of just failing. */ gem_rxdrain(sc); return (1); @@ -929,8 +881,7 @@ gem_meminit(sc) } static u_int -gem_ringsize(sz) - u_int sz; +gem_ringsize(u_int sz) { switch (sz) { @@ -959,10 +910,9 @@ gem_ringsize(sz) } static void -gem_init(xsc) - void *xsc; +gem_init(void *xsc) { - struct gem_softc *sc = (struct gem_softc *)xsc; + struct gem_softc *sc = xsc; GEM_LOCK(sc); gem_init_locked(sc); @@ -974,11 +924,10 @@ gem_init(xsc) * and transmit/receive descriptor rings. */ static void -gem_init_locked(sc) - struct gem_softc *sc; +gem_init_locked(struct gem_softc *sc) { struct ifnet *ifp = sc->sc_ifp; - u_int32_t v; + uint32_t v; GEM_LOCK_ASSERT(sc, MA_OWNED); @@ -987,13 +936,13 @@ gem_init_locked(sc) __func__); #endif /* - * Initialization sequence. The numbered steps below correspond + * Initialization sequence. The numbered steps below correspond * to the sequence outlined in section 6.3.5.1 in the Ethernet * Channel Engine manual (part of the PCIO manual). * See also the STP2002-STQ document from Sun Microsystems. */ - /* step 1 & 2. Reset the Ethernet Channel */ + /* step 1 & 2. Reset the Ethernet Channel. */ gem_stop(sc->sc_ifp, 0); gem_reset(sc); #ifdef GEM_DEBUG @@ -1001,20 +950,20 @@ gem_init_locked(sc) __func__); #endif - /* Re-initialize the MIF */ + /* Re-initialize the MIF. */ gem_mifinit(sc); - /* step 3. Setup data structures in host memory */ + /* step 3. Setup data structures in host memory. */ if (gem_meminit(sc) != 0) return; - /* step 4. TX MAC registers & counters */ + /* step 4. TX MAC registers & counters */ gem_init_regs(sc); - /* step 5. RX MAC registers & counters */ + /* step 5. RX MAC registers & counters */ gem_setladrf(sc); - /* step 6 & 7. Program Descriptor Ring Base Addresses */ + /* step 6 & 7. Program Descriptor Ring Base Addresses. */ /* NOTE: we use only 32-bit DMA addresses here. */ bus_write_4(sc->sc_res[0], GEM_TX_RING_PTR_HI, 0); bus_write_4(sc->sc_res[0], GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0)); @@ -1022,11 +971,11 @@ gem_init_locked(sc) bus_write_4(sc->sc_res[0], GEM_RX_RING_PTR_HI, 0); bus_write_4(sc->sc_res[0], GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); #ifdef GEM_DEBUG - CTR3(KTR_GEM, "loading rx ring %lx, tx ring %lx, cddma %lx", + CTR3(KTR_GEM, "loading RX ring %lx, TX ring %lx, cddma %lx", GEM_CDRXADDR(sc, 0), GEM_CDTXADDR(sc, 0), sc->sc_cddma); #endif - /* step 8. Global Configuration & Interrupt Mask */ + /* step 8. Global Configuration & Interrupt Mask */ bus_write_4(sc->sc_res[0], GEM_INTMASK, ~(GEM_INTR_TX_INTME | GEM_INTR_TX_EMPTY | GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF | GEM_INTR_RX_TAG_ERR | GEM_INTR_PERR | @@ -1047,26 +996,26 @@ gem_init_locked(sc) GEM_MAC_PAUSED | GEM_MAC_PAUSE | GEM_MAC_RESUME); #endif - /* step 9. ETX Configuration: use mostly default values */ + /* step 9. ETX Configuration: use mostly default values. */ - /* Enable DMA */ - v = gem_ringsize(GEM_NTXDESC /*XXX*/); + /* Enable DMA. */ + v = gem_ringsize(GEM_NTXDESC /* XXX */); bus_write_4(sc->sc_res[0], GEM_TX_CONFIG, - v|GEM_TX_CONFIG_TXDMA_EN| - ((0x400<<10)&GEM_TX_CONFIG_TXFIFO_TH)); + v | GEM_TX_CONFIG_TXDMA_EN | + ((0x400 << 10) & GEM_TX_CONFIG_TXFIFO_TH)); - /* step 10. ERX Configuration */ + /* step 10. ERX Configuration */ /* Encode Receive Descriptor ring size. */ - v = gem_ringsize(GEM_NRXDESC /*XXX*/); - /* Rx TCP/UDP checksum offset */ + v = gem_ringsize(GEM_NRXDESC /* XXX */); + /* RX TCP/UDP checksum offset */ v |= ((ETHER_HDR_LEN + sizeof(struct ip)) << GEM_RX_CONFIG_CXM_START_SHFT); - /* Enable DMA */ + /* Enable DMA. */ bus_write_4(sc->sc_res[0], GEM_RX_CONFIG, - v|(GEM_THRSH_1024<sc_res[0], GEM_RX_BLANKING, (6 << GEM_RX_BLANKING_TIME_SHIFT) | 6); @@ -1077,11 +1026,11 @@ gem_init_locked(sc) */ bus_write_4(sc->sc_res[0], GEM_RX_PAUSE_THRESH, (3 * sc->sc_rxfifosize / 256) | - ( (sc->sc_rxfifosize / 256) << 12)); + ((sc->sc_rxfifosize / 256) << 12)); - /* step 11. Configure Media */ + /* step 11. Configure Media. */ - /* step 12. RX_MAC Configuration Register */ + /* step 12. RX_MAC Configuration Register */ v = bus_read_4(sc->sc_res[0], GEM_MAC_RX_CONFIG); v |= GEM_MAC_RX_STRIP_CRC; bus_write_4(sc->sc_res[0], GEM_MAC_RX_CONFIG, 0); @@ -1091,10 +1040,10 @@ gem_init_locked(sc) device_printf(sc->sc_dev, "cannot disable RX MAC\n"); bus_write_4(sc->sc_res[0], GEM_MAC_RX_CONFIG, v); - /* step 14. Issue Transmit Pending command */ + /* step 14. Issue Transmit Pending command. */ - /* step 15. Give the reciever a swift kick */ - bus_write_4(sc->sc_res[0], GEM_RX_KICK, GEM_NRXDESC-4); + /* step 15. Give the reciever a swift kick. */ + bus_write_4(sc->sc_res[0], GEM_RX_KICK, GEM_NRXDESC - 4); ifp->if_drv_flags |= IFF_DRV_RUNNING; ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; @@ -1109,7 +1058,7 @@ gem_init_locked(sc) } /* - * It's copy of ath_defrag(ath(4)). + * This is a copy of ath_defrag(ath(4)). * * Defragment an mbuf chain, returning at most maxfrags separate * mbufs+clusters. If this is not possible NULL is returned and @@ -1118,10 +1067,7 @@ gem_init_locked(sc) * mbufs and replacing consecutive mbufs by a cluster. */ static struct mbuf * -gem_defrag(m0, how, maxfrags) - struct mbuf *m0; - int how; - int maxfrags; +gem_defrag(struct mbuf *m0, int how, int maxfrags) { struct mbuf *m, *n, *n2, **prev; u_int curfrags; @@ -1139,7 +1085,7 @@ gem_defrag(m0, how, maxfrags) * less data than the following. */ m = m0; -again: + again: for (;;) { n = m->m_next; if (n == NULL) @@ -1157,11 +1103,11 @@ gem_defrag(m0, how, maxfrags) m = n; } KASSERT(maxfrags > 1, - ("maxfrags %u, but normal collapse failed", maxfrags)); + ("maxfrags %u, but normal collapse failed", maxfrags)); /* * Collapse consecutive mbufs to a cluster. */ - prev = &m0->m_next; /* NB: not the first mbuf */ + prev = &m0->m_next; /* NB: not the first mbuf. */ while ((n = *prev) != NULL) { if ((n2 = n->m_next) != NULL && n->m_len + n2->m_len < MCLBYTES) { @@ -1177,7 +1123,7 @@ gem_defrag(m0, how, maxfrags) m_free(n); m_free(n2); if (--curfrags <= maxfrags) /* +1 cl -2 mbufs */ - return m0; + return (m0); /* * Still not there, try the normal collapse * again before we allocate another cluster. @@ -1193,19 +1139,17 @@ gem_defrag(m0, how, maxfrags) * never reallocate the first mbuf to avoid moving the * packet header). */ -bad: + bad: return (NULL); } static int -gem_load_txmbuf(sc, m_head) - struct gem_softc *sc; - struct mbuf **m_head; +gem_load_txmbuf(struct gem_softc *sc, struct mbuf **m_head) { - struct gem_txsoft *txs; bus_dma_segment_t txsegs[GEM_NTXSEGS]; + struct gem_txsoft *txs; struct mbuf *m; - uint64_t flags, cflags; + uint64_t cflags, flags; int error, nexttx, nsegs, seg; /* Get a work queue entry. */ @@ -1223,8 +1167,9 @@ gem_load_txmbuf(sc, m_head) return (ENOBUFS); } *m_head = m; - error = bus_dmamap_load_mbuf_sg(sc->sc_tdmatag, txs->txs_dmamap, - *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT); + error = bus_dmamap_load_mbuf_sg(sc->sc_tdmatag, + txs->txs_dmamap, *m_head, txsegs, &nsegs, + BUS_DMA_NOWAIT); if (error != 0) { m_freem(*m_head); *m_head = NULL; @@ -1241,8 +1186,8 @@ gem_load_txmbuf(sc, m_head) /* * Ensure we have enough descriptors free to describe * the packet. Note, we always reserve one descriptor - * at the end of the ring as a termination point, to - * prevent wrap-around. + * at the end of the ring as a termination point, in + * order to prevent wrap-around. */ if (nsegs > sc->sc_txfree - 1) { txs->txs_ndescs = 0; @@ -1259,9 +1204,10 @@ gem_load_txmbuf(sc, m_head) nexttx = txs->txs_firstdesc; for (seg = 0; seg < nsegs; seg++, nexttx = GEM_NEXTTX(nexttx)) { #ifdef GEM_DEBUG - CTR6(KTR_GEM, "%s: mapping seg %d (txd %d), len " - "%lx, addr %#lx (%#lx)", __func__, seg, nexttx, - txsegs[seg].ds_len, txsegs[seg].ds_addr, + CTR6(KTR_GEM, + "%s: mapping seg %d (txd %d), len %lx, addr %#lx (%#lx)", + __func__, seg, nexttx, txsegs[seg].ds_len, + txsegs[seg].ds_addr, GEM_DMA_WRITE(sc, txsegs[seg].ds_addr)); #endif sc->sc_txdescs[nexttx].gd_addr = @@ -1274,18 +1220,18 @@ gem_load_txmbuf(sc, m_head) txs->txs_lastdesc = nexttx; } - /* set EOP on the last descriptor */ + /* Set EOP on the last descriptor. */ #ifdef GEM_DEBUG - CTR3(KTR_GEM, "%s: end of packet at seg %d, tx %d", __func__, seg, - nexttx); + CTR3(KTR_GEM, "%s: end of packet at segment %d, TX %d", + __func__, seg, nexttx); #endif sc->sc_txdescs[txs->txs_lastdesc].gd_flags |= GEM_DMA_WRITE(sc, GEM_TD_END_OF_PACKET); - /* Lastly set SOP on the first descriptor */ + /* Lastly set SOP on the first descriptor. */ #ifdef GEM_DEBUG - CTR3(KTR_GEM, "%s: start of packet at seg %d, tx %d", __func__, seg, - nexttx); + CTR3(KTR_GEM, "%s: start of packet at segment %d, TX %d", + __func__, seg, nexttx); #endif if (++sc->sc_txwin > GEM_NTXSEGS * 2 / 3) { sc->sc_txwin = 0; @@ -1298,11 +1244,13 @@ gem_load_txmbuf(sc, m_head) GEM_DMA_WRITE(sc, GEM_TD_START_OF_PACKET); /* Sync the DMA map. */ - bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, BUS_DMASYNC_PREWRITE); + bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, + BUS_DMASYNC_PREWRITE); #ifdef GEM_DEBUG CTR4(KTR_GEM, "%s: setting firstdesc=%d, lastdesc=%d, ndescs=%d", - __func__, txs->txs_firstdesc, txs->txs_lastdesc, txs->txs_ndescs); + __func__, txs->txs_firstdesc, txs->txs_lastdesc, + txs->txs_ndescs); #endif STAILQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); STAILQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); @@ -1315,42 +1263,42 @@ gem_load_txmbuf(sc, m_head) } static void -gem_init_regs(sc) - struct gem_softc *sc; +gem_init_regs(struct gem_softc *sc) { const u_char *laddr = IF_LLADDR(sc->sc_ifp); - /* These regs are not cleared on reset */ + /* These registers are not cleared on reset. */ if ((sc->sc_flags & GEM_INITED) == 0) { - /* Wooo. Magic values. */ + /* magic values */ bus_write_4(sc->sc_res[0], GEM_MAC_IPG0, 0); bus_write_4(sc->sc_res[0], GEM_MAC_IPG1, 8); bus_write_4(sc->sc_res[0], GEM_MAC_IPG2, 4); - bus_write_4(sc->sc_res[0], GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); - /* Max frame and max burst size */ + bus_write_4(sc->sc_res[0], GEM_MAC_MAC_MIN_FRAME, + ETHER_MIN_LEN); + /* max frame and max burst size */ bus_write_4(sc->sc_res[0], GEM_MAC_MAC_MAX_FRAME, (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) | (0x2000 << 16)); bus_write_4(sc->sc_res[0], GEM_MAC_PREAMBLE_LEN, 0x7); bus_write_4(sc->sc_res[0], GEM_MAC_JAM_SIZE, 0x4); bus_write_4(sc->sc_res[0], GEM_MAC_ATTEMPT_LIMIT, 0x10); - /* Dunno.... */ + /* dunno... */ bus_write_4(sc->sc_res[0], GEM_MAC_CONTROL_TYPE, 0x8088); bus_write_4(sc->sc_res[0], GEM_MAC_RANDOM_SEED, - ((laddr[5]<<8)|laddr[4])&0x3ff); + ((laddr[5] << 8) | laddr[4]) & 0x3ff); - /* Secondary MAC addr set to 0:0:0:0:0:0 */ + /* secondary MAC address: 0:0:0:0:0:0 */ bus_write_4(sc->sc_res[0], GEM_MAC_ADDR3, 0); bus_write_4(sc->sc_res[0], GEM_MAC_ADDR4, 0); bus_write_4(sc->sc_res[0], GEM_MAC_ADDR5, 0); - /* MAC control addr set to 01:80:c2:00:00:01 */ + /* MAC control address: 01:80:c2:00:00:01 */ bus_write_4(sc->sc_res[0], GEM_MAC_ADDR6, 0x0001); bus_write_4(sc->sc_res[0], GEM_MAC_ADDR7, 0xc200); bus_write_4(sc->sc_res[0], GEM_MAC_ADDR8, 0x0180); - /* MAC filter addr set to 0:0:0:0:0:0 */ + /* MAC filter address: 0:0:0:0:0:0 */ bus_write_4(sc->sc_res[0], GEM_MAC_ADDR_FILTER0, 0); bus_write_4(sc->sc_res[0], GEM_MAC_ADDR_FILTER1, 0); bus_write_4(sc->sc_res[0], GEM_MAC_ADDR_FILTER2, 0); @@ -1361,7 +1309,7 @@ gem_init_regs(sc) sc->sc_flags |= GEM_INITED; } - /* Counters need to be zeroed */ + /* Counters need to be zeroed. */ bus_write_4(sc->sc_res[0], GEM_MAC_NORM_COLL_CNT, 0); bus_write_4(sc->sc_res[0], GEM_MAC_FIRST_COLL_CNT, 0); bus_write_4(sc->sc_res[0], GEM_MAC_EXCESS_COLL_CNT, 0); @@ -1380,7 +1328,7 @@ gem_init_regs(sc) /* * Set the internal arbitration to "infinite" bursts of the * maximum length of 31 * 64 bytes so DMA transfers aren't - * split up in cache line size chunks. This greatly improves + * split up in cache line size chunks. This greatly improves * especially RX performance. * Enable silicon bug workarounds for the Apple variants. */ @@ -1389,22 +1337,23 @@ gem_init_regs(sc) GEM_CONFIG_BURST_INF | (GEM_IS_APPLE(sc) ? GEM_CONFIG_RONPAULBIT | GEM_CONFIG_BUG2FIX : 0)); - /* - * Set the station address. - */ - bus_write_4(sc->sc_res[0], GEM_MAC_ADDR0, (laddr[4]<<8)|laddr[5]); - bus_write_4(sc->sc_res[0], GEM_MAC_ADDR1, (laddr[2]<<8)|laddr[3]); - bus_write_4(sc->sc_res[0], GEM_MAC_ADDR2, (laddr[0]<<8)|laddr[1]); + /* Set the station address. */ + bus_write_4(sc->sc_res[0], GEM_MAC_ADDR0, + (laddr[4] << 8) | laddr[5]); + bus_write_4(sc->sc_res[0], GEM_MAC_ADDR1, + (laddr[2] << 8) | laddr[3]); + bus_write_4(sc->sc_res[0], GEM_MAC_ADDR2, + (laddr[0] << 8) | laddr[1]); /* Enable MII outputs. */ - bus_write_4(sc->sc_res[0], GEM_MAC_XIF_CONFIG, GEM_MAC_XIF_TX_MII_ENA); + bus_write_4(sc->sc_res[0], GEM_MAC_XIF_CONFIG, + GEM_MAC_XIF_TX_MII_ENA); } static void -gem_start(ifp) - struct ifnet *ifp; +gem_start(struct ifnet *ifp) { - struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; + struct gem_softc *sc = ifp->if_softc; GEM_LOCK(sc); gem_start_locked(ifp); @@ -1412,12 +1361,11 @@ gem_start(ifp) } static void -gem_start_locked(ifp) - struct ifnet *ifp; +gem_start_locked(struct ifnet *ifp) { - struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; + struct gem_softc *sc = ifp->if_softc; struct mbuf *m; - int ntx = 0; + int ntx; if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != IFF_DRV_RUNNING || (sc->sc_flags & GEM_LINK) == 0) @@ -1428,6 +1376,7 @@ gem_start_locked(ifp) device_get_name(sc->sc_dev), __func__, sc->sc_txfree, sc->sc_txnext); #endif + ntx = 0; for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && sc->sc_txfree > 1;) { IFQ_DRV_DEQUEUE(&ifp->if_snd, m); if (m == NULL) @@ -1442,12 +1391,11 @@ gem_start_locked(ifp) ntx++; /* Kick the transmitter. */ #ifdef GEM_DEBUG - CTR3(KTR_GEM, "%s: %s: kicking tx %d", + CTR3(KTR_GEM, "%s: %s: kicking TX %d", device_get_name(sc->sc_dev), __func__, sc->sc_txnext); #endif GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE); - bus_write_4(sc->sc_res[0], GEM_TX_KICK, - sc->sc_txnext); + bus_write_4(sc->sc_res[0], GEM_TX_KICK, sc->sc_txnext); BPF_MTAP(ifp, m); } @@ -1462,44 +1410,43 @@ gem_start_locked(ifp) sc->sc_wdog_timer = 5; #ifdef GEM_DEBUG CTR3(KTR_GEM, "%s: %s: watchdog %d", - device_get_name(sc->sc_dev), __func__, sc->sc_wdog_timer); + device_get_name(sc->sc_dev), __func__, + sc->sc_wdog_timer); #endif } } -/* - * Transmit interrupt. - */ static void -gem_tint(sc) - struct gem_softc *sc; +gem_tint(struct gem_softc *sc) { struct ifnet *ifp = sc->sc_ifp; struct gem_txsoft *txs; - int txlast; - int progress = 0; - + int txlast, progress; #ifdef GEM_DEBUG + int i; + CTR2(KTR_GEM, "%s: %s", device_get_name(sc->sc_dev), __func__); #endif /* - * Go through our Tx list and free mbufs for those + * Go through our TX list and free mbufs for those * frames that have been transmitted. */ + progress = 0; GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD); while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { #ifdef GEM_DEBUG - if (ifp->if_flags & IFF_DEBUG) { - int i; + if ((ifp->if_flags & IFF_DEBUG) != 0) { printf(" txsoft %p transmit chain:\n", txs); for (i = txs->txs_firstdesc;; i = GEM_NEXTTX(i)) { printf("descriptor %d: ", i); - printf("gd_flags: 0x%016llx\t", (long long) - GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_flags)); - printf("gd_addr: 0x%016llx\n", (long long) - GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_addr)); + printf("gd_flags: 0x%016llx\t", + (long long)GEM_DMA_READ(sc, + sc->sc_txdescs[i].gd_flags)); + printf("gd_addr: 0x%016llx\n", + (long long)GEM_DMA_READ(sc, + sc->sc_txdescs[i].gd_addr)); if (i == txs->txs_lastdesc) break; } @@ -1511,7 +1458,7 @@ gem_tint(sc) * the ring is empty, but that's a bit complicated. * * GEM_TX_COMPLETION points to the last descriptor - * processed +1. + * processed + 1. */ txlast = bus_read_4(sc->sc_res[0], GEM_TX_COMPLETION); #ifdef GEM_DEBUG @@ -1521,17 +1468,17 @@ gem_tint(sc) #endif if (txs->txs_firstdesc <= txs->txs_lastdesc) { if ((txlast >= txs->txs_firstdesc) && - (txlast <= txs->txs_lastdesc)) + (txlast <= txs->txs_lastdesc)) break; } else { - /* Ick -- this command wraps */ + /* Ick -- this command wraps. */ if ((txlast >= txs->txs_firstdesc) || - (txlast <= txs->txs_lastdesc)) + (txlast <= txs->txs_lastdesc)) break; } #ifdef GEM_DEBUG - CTR1(KTR_GEM, "%s: releasing a desc", __func__); + CTR1(KTR_GEM, "%s: releasing a descriptor", __func__); #endif STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); @@ -1552,12 +1499,11 @@ gem_tint(sc) } #ifdef GEM_DEBUG - CTR4(KTR_GEM, "%s: GEM_TX_STATE_MACHINE %x " - "GEM_TX_DATA_PTR %llx " + CTR4(KTR_GEM, "%s: GEM_TX_STATE_MACHINE %x GEM_TX_DATA_PTR %llx " "GEM_TX_COMPLETION %x", - __func__, - bus_read_4(sc->sc_res[0], GEM_TX_STATE_MACHINE), - ((long long) bus_read_4(sc->sc_res[0], GEM_TX_DATA_PTR_HI) << 32) | + __func__, bus_read_4(sc->sc_res[0], GEM_TX_STATE_MACHINE), + ((long long)bus_read_4(sc->sc_res[0], + GEM_TX_DATA_PTR_HI) << 32) | bus_read_4(sc->sc_res[0], GEM_TX_DATA_PTR_LO), bus_read_4(sc->sc_res[0], GEM_TX_COMPLETION)); #endif @@ -1566,7 +1512,10 @@ gem_tint(sc) if (sc->sc_txfree == GEM_NTXDESC - 1) sc->sc_txwin = 0; - /* Freed some descriptors, so reset IFF_DRV_OACTIVE and restart. */ + /* + * We freed some descriptors, so reset IFF_DRV_OACTIVE + * and restart. + */ ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; sc->sc_wdog_timer = STAILQ_EMPTY(&sc->sc_txdirtyq) ? 0 : 5; @@ -1583,27 +1532,22 @@ gem_tint(sc) #ifdef GEM_RINT_TIMEOUT static void -gem_rint_timeout(arg) - void *arg; +gem_rint_timeout(void *arg) { - struct gem_softc *sc = (struct gem_softc *)arg; + struct gem_softc *sc = arg; GEM_LOCK_ASSERT(sc, MA_OWNED); gem_rint(sc); } #endif -/* - * Receive interrupt. - */ static void -gem_rint(sc) - struct gem_softc *sc; +gem_rint(struct gem_softc *sc) { struct ifnet *ifp = sc->sc_ifp; struct mbuf *m; - u_int64_t rxstat; - u_int32_t rxcomp; + uint64_t rxstat; + uint32_t rxcomp; #ifdef GEM_RINT_TIMEOUT callout_stop(&sc->sc_rx_ch); @@ -1632,8 +1576,8 @@ gem_rint(sc) #ifdef GEM_RINT_TIMEOUT /* * The descriptor is still marked as owned, although - * it is supposed to have completed. This has been - * observed on some machines. Just exiting here + * it is supposed to have completed. This has been + * observed on some machines. Just exiting here * might leave the packet sitting around until another * one arrives to trigger a new interrupt, which is * generally undesirable, so set up a timeout. @@ -1654,15 +1598,15 @@ gem_rint(sc) } #ifdef GEM_DEBUG - if (ifp->if_flags & IFF_DEBUG) { + if ((ifp->if_flags & IFF_DEBUG) != 0) { printf(" rxsoft %p descriptor %d: ", &sc->sc_rxsoft[sc->sc_rxptr], sc->sc_rxptr); - printf("gd_flags: 0x%016llx\t", (long long) - GEM_DMA_READ(sc, sc->sc_rxdescs[ - sc->sc_rxptr].gd_flags)); - printf("gd_addr: 0x%016llx\n", (long long) - GEM_DMA_READ(sc, sc->sc_rxdescs[ - sc->sc_rxptr].gd_addr)); + printf("gd_flags: 0x%016llx\t", + (long long)GEM_DMA_READ(sc, + sc->sc_rxdescs[sc->sc_rxptr].gd_flags)); + printf("gd_addr: 0x%016llx\n", + (long long)GEM_DMA_READ(sc, + sc->sc_rxdescs[sc->sc_rxptr].gd_addr)); } #endif @@ -1677,9 +1621,9 @@ gem_rint(sc) m = NULL; } -kickit: - /* - * Update the RX kick register. This register has to point + kickit: + /* + * Update the RX kick register. This register has to point * to the descriptor after the last valid one (before the * current batch) and must be incremented in multiples of * 4 (because the DMA engine fetches/updates descriptors @@ -1715,19 +1659,12 @@ gem_rint(sc) #ifdef GEM_DEBUG CTR3(KTR_GEM, "%s: done sc->rxptr %d, complete %d", __func__, - sc->sc_rxptr, bus_read_4(sc->sc_res[0], GEM_RX_COMPLETION)); + sc->sc_rxptr, bus_read_4(sc->sc_res[0], GEM_RX_COMPLETION)); #endif } -/* - * gem_add_rxbuf: - * - * Add a receive buffer to the indicated descriptor. - */ static int -gem_add_rxbuf(sc, idx) - struct gem_softc *sc; - int idx; +gem_add_rxbuf(struct gem_softc *sc, int idx) { struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx]; struct mbuf *m; @@ -1740,7 +1677,7 @@ gem_add_rxbuf(sc, idx) m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; #ifdef GEM_DEBUG - /* bzero the packet to check dma */ + /* Bzero the packet to check DMA. */ memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size); #endif @@ -1752,18 +1689,19 @@ gem_add_rxbuf(sc, idx) error = bus_dmamap_load_mbuf_sg(sc->sc_rdmatag, rxs->rxs_dmamap, m, segs, &nsegs, BUS_DMA_NOWAIT); - /* If nsegs is wrong then the stack is corrupt. */ KASSERT(nsegs == 1, ("Too many segments returned!")); if (error != 0) { - device_printf(sc->sc_dev, "can't load rx DMA map %d, error = " - "%d\n", idx, error); + device_printf(sc->sc_dev, + "cannot load RS DMA map %d, error = %d\n", idx, error); m_freem(m); return (error); } + /* If nsegs is wrong then the stack is corrupt. */ rxs->rxs_mbuf = m; rxs->rxs_paddr = segs[0].ds_addr; - bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap, BUS_DMASYNC_PREREAD); + bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap, + BUS_DMASYNC_PREREAD); GEM_INIT_RXDESC(sc, idx); @@ -1771,9 +1709,7 @@ gem_add_rxbuf(sc, idx) } static void -gem_eint(sc, status) - struct gem_softc *sc; - u_int status; +gem_eint(struct gem_softc *sc, u_int status) { sc->sc_ifp->if_ierrors++; @@ -1786,10 +1722,9 @@ gem_eint(sc, status) } void -gem_intr(v) - void *v; +gem_intr(void *v) { - struct gem_softc *sc = (struct gem_softc *)v; + struct gem_softc *sc = v; uint32_t status, status2; GEM_LOCK(sc); @@ -1797,14 +1732,15 @@ gem_intr(v) #ifdef GEM_DEBUG CTR4(KTR_GEM, "%s: %s: cplt %x, status %x", - device_get_name(sc->sc_dev), __func__, (status>>19), - (u_int)status); + device_get_name(sc->sc_dev), __func__, (status >> 19), + (u_int)status); /* * PCS interrupts must be cleared, otherwise no traffic is passed! */ if ((status & GEM_INTR_PCS) != 0) { - status2 = bus_read_4(sc->sc_res[0], GEM_MII_INTERRUP_STATUS) | + status2 = + bus_read_4(sc->sc_res[0], GEM_MII_INTERRUP_STATUS) | bus_read_4(sc->sc_res[0], GEM_MII_INTERRUP_STATUS); if ((status2 & GEM_MII_INTERRUP_LINK) != 0) device_printf(sc->sc_dev, @@ -1839,10 +1775,12 @@ gem_intr(v) if (status & GEM_INTR_TX_MAC) { status2 = bus_read_4(sc->sc_res[0], GEM_MAC_TX_STATUS); - if (status2 & ~(GEM_MAC_TX_XMIT_DONE | GEM_MAC_TX_DEFER_EXP)) - device_printf(sc->sc_dev, "MAC tx fault, status %x\n", - status2); - if (status2 & (GEM_MAC_TX_UNDERRUN | GEM_MAC_TX_PKT_TOO_LONG)) + if ((status2 & + ~(GEM_MAC_TX_XMIT_DONE | GEM_MAC_TX_DEFER_EXP)) != 0) + device_printf(sc->sc_dev, + "MAC TX fault, status %x\n", status2); + if ((status2 & + (GEM_MAC_TX_UNDERRUN | GEM_MAC_TX_PKT_TOO_LONG)) != 0) gem_init_locked(sc); } if (status & GEM_INTR_RX_MAC) { @@ -1850,37 +1788,37 @@ gem_intr(v) /* * At least with GEM_SUN_GEM and some GEM_SUN_ERI * revisions GEM_MAC_RX_OVERFLOW happen often due to a - * silicon bug so handle them silently. Moreover, it's + * silicon bug so handle them silently. Moreover, it's * likely that the receiver has hung so we reset it. */ - if (status2 & GEM_MAC_RX_OVERFLOW) { + if ((status2 & GEM_MAC_RX_OVERFLOW) != 0) { sc->sc_ifp->if_ierrors++; gem_reset_rxdma(sc); - } else if (status2 & ~(GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT)) - device_printf(sc->sc_dev, "MAC rx fault, status %x\n", - status2); + } else if ((status2 & + ~(GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT)) != 0) + device_printf(sc->sc_dev, + "MAC RX fault, status %x\n", status2); } GEM_UNLOCK(sc); } static int -gem_watchdog(sc) - struct gem_softc *sc; +gem_watchdog(struct gem_softc *sc) { GEM_LOCK_ASSERT(sc, MA_OWNED); #ifdef GEM_DEBUG - CTR4(KTR_GEM, "%s: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x " - "GEM_MAC_RX_CONFIG %x", __func__, - bus_read_4(sc->sc_res[0], GEM_RX_CONFIG), - bus_read_4(sc->sc_res[0], GEM_MAC_RX_STATUS), - bus_read_4(sc->sc_res[0], GEM_MAC_RX_CONFIG)); - CTR4(KTR_GEM, "%s: GEM_TX_CONFIG %x GEM_MAC_TX_STATUS %x " - "GEM_MAC_TX_CONFIG %x", __func__, - bus_read_4(sc->sc_res[0], GEM_TX_CONFIG), - bus_read_4(sc->sc_res[0], GEM_MAC_TX_STATUS), - bus_read_4(sc->sc_res[0], GEM_MAC_TX_CONFIG)); + CTR4(KTR_GEM, + "%s: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x GEM_MAC_RX_CONFIG %x", + __func__, bus_read_4(sc->sc_res[0], GEM_RX_CONFIG), + bus_read_4(sc->sc_res[0], GEM_MAC_RX_STATUS), + bus_read_4(sc->sc_res[0], GEM_MAC_RX_CONFIG)); + CTR4(KTR_GEM, + "%s: GEM_TX_CONFIG %x GEM_MAC_TX_STATUS %x GEM_MAC_TX_CONFIG %x", + __func__, bus_read_4(sc->sc_res[0], GEM_TX_CONFIG), + bus_read_4(sc->sc_res[0], GEM_MAC_TX_STATUS), + bus_read_4(sc->sc_res[0], GEM_MAC_TX_CONFIG)); #endif if (sc->sc_wdog_timer == 0 || --sc->sc_wdog_timer != 0) @@ -1897,12 +1835,8 @@ gem_watchdog(sc) return (EJUSTRETURN); } -/* - * Initialize the MII Management Interface - */ static void -gem_mifinit(sc) - struct gem_softc *sc; +gem_mifinit(struct gem_softc *sc) { /* Configure the MIF in frame mode */ @@ -1925,18 +1859,17 @@ gem_mifinit(sc) * */ int -gem_mii_readreg(dev, phy, reg) - device_t dev; - int phy, reg; +gem_mii_readreg(device_t dev, int phy, int reg) { - struct gem_softc *sc = device_get_softc(dev); + struct gem_softc *sc; int n; - u_int32_t v; + uint32_t v; #ifdef GEM_DEBUG_PHY printf("%s: phy %d reg %d\n", __func__, phy, reg); #endif + sc = device_get_softc(dev); if (sc->sc_phyad != -1 && phy != sc->sc_phyad) return (0); @@ -1967,7 +1900,7 @@ gem_mii_readreg(dev, phy, reg) return (bus_read_4(sc->sc_res[0], reg)); } - /* Construct the frame command */ + /* Construct the frame command. */ v = GEM_MIF_FRAME_READ | (phy << GEM_MIF_PHY_SHIFT) | (reg << GEM_MIF_REG_SHIFT); @@ -1980,23 +1913,22 @@ gem_mii_readreg(dev, phy, reg) return (v & GEM_MIF_FRAME_DATA); } - device_printf(sc->sc_dev, "mii_read timeout\n"); + device_printf(sc->sc_dev, "%s: timed out\n", __func__); return (0); } int -gem_mii_writereg(dev, phy, reg, val) - device_t dev; - int phy, reg, val; +gem_mii_writereg(device_t dev, int phy, int reg, int val) { - struct gem_softc *sc = device_get_softc(dev); + struct gem_softc *sc; int n; - u_int32_t v; + uint32_t v; #ifdef GEM_DEBUG_PHY printf("%s: phy %d reg %d val %x\n", phy, reg, val, __func__); #endif + sc = device_get_softc(dev); if (sc->sc_phyad != -1 && phy != sc->sc_phyad) return (0); @@ -2030,7 +1962,7 @@ gem_mii_writereg(dev, phy, reg, val) return (0); } - /* Construct the frame command */ + /* Construct the frame command. */ v = GEM_MIF_FRAME_WRITE | (phy << GEM_MIF_PHY_SHIFT) | (reg << GEM_MIF_REG_SHIFT) | @@ -2044,20 +1976,21 @@ gem_mii_writereg(dev, phy, reg, val) return (1); } - device_printf(sc->sc_dev, "mii_write timeout\n"); + device_printf(sc->sc_dev, "%s: timed out\n", __func__); return (0); } void -gem_mii_statchg(dev) - device_t dev; +gem_mii_statchg(device_t dev) { - struct gem_softc *sc = device_get_softc(dev); + struct gem_softc *sc; int gigabit; uint32_t rxcfg, txcfg, v; + sc = device_get_softc(dev); + #ifdef GEM_DEBUG - if ((sc->sc_ifflags & IFF_DEBUG) != 0) + if ((sc->sc_ifp->if_flags & IFF_DEBUG) != 0) device_printf(sc->sc_dev, "%s: status change: PHY = %d\n", __func__, sc->sc_phyad); #endif @@ -2111,9 +2044,11 @@ gem_mii_statchg(dev) v = bus_read_4(sc->sc_res[0], GEM_MAC_CONTROL_CONFIG) & ~(GEM_MAC_CC_RX_PAUSE | GEM_MAC_CC_TX_PAUSE); #ifdef notyet - if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) + if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & + IFM_ETH_RXPAUSE) != 0) v |= GEM_MAC_CC_RX_PAUSE; - if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) + if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & + IFM_ETH_TXPAUSE) != 0) v |= GEM_MAC_CC_TX_PAUSE; #endif bus_write_4(sc->sc_res[0], GEM_MAC_CONTROL_CONFIG, v); @@ -2132,9 +2067,10 @@ gem_mii_statchg(dev) if ((sc->sc_flags & GEM_SERDES) == 0) { if ((bus_read_4(sc->sc_res[0], GEM_MIF_CONFIG) & GEM_MIF_CONFIG_PHY_SEL) != 0 && - (IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0) + (IFM_OPTIONS(sc->sc_mii->mii_media_active) & + IFM_FDX) == 0) /* External MII needs echo disable if half duplex. */ - v |= GEM_MAC_XIF_ECHO_DISABL; + v |= GEM_MAC_XIF_ECHO_DISABL; else /* * Internal MII needs buffer enable. @@ -2159,13 +2095,12 @@ gem_mii_statchg(dev) } int -gem_mediachange(ifp) - struct ifnet *ifp; +gem_mediachange(struct ifnet *ifp) { struct gem_softc *sc = ifp->if_softc; int error; - /* XXX Add support for serial media. */ + /* XXX add support for serial media. */ GEM_LOCK(sc); error = mii_mediachg(sc->sc_mii); @@ -2174,9 +2109,7 @@ gem_mediachange(ifp) } void -gem_mediastatus(ifp, ifmr) - struct ifnet *ifp; - struct ifmediareq *ifmr; +gem_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) { struct gem_softc *sc = ifp->if_softc; @@ -2192,33 +2125,26 @@ gem_mediastatus(ifp, ifmr) GEM_UNLOCK(sc); } -/* - * Process an ioctl request. - */ static int -gem_ioctl(ifp, cmd, data) - struct ifnet *ifp; - u_long cmd; - caddr_t data; +gem_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) { struct gem_softc *sc = ifp->if_softc; struct ifreq *ifr = (struct ifreq *)data; - int error = 0; + int error; + error = 0; switch (cmd) { case SIOCSIFFLAGS: GEM_LOCK(sc); - if (ifp->if_flags & IFF_UP) { + if ((ifp->if_flags & IFF_UP) != 0) { if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && ((ifp->if_flags ^ sc->sc_ifflags) & (IFF_ALLMULTI | IFF_PROMISC)) != 0) gem_setladrf(sc); else gem_init_locked(sc); - } else { - if (ifp->if_drv_flags & IFF_DRV_RUNNING) - gem_stop(ifp, 0); - } + } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) + gem_stop(ifp, 0); if ((ifp->if_flags & IFF_LINK0) != 0) sc->sc_csum_features |= CSUM_UDP; else @@ -2255,23 +2181,18 @@ gem_ioctl(ifp, cmd, data) return (error); } -/* - * Set up the logical address filter. - */ static void -gem_setladrf(sc) - struct gem_softc *sc; +gem_setladrf(struct gem_softc *sc) { struct ifnet *ifp = sc->sc_ifp; struct ifmultiaddr *inm; - u_int32_t crc; - u_int32_t hash[16]; - u_int32_t v; int i; + uint32_t hash[16]; + uint32_t crc, v; GEM_LOCK_ASSERT(sc, MA_OWNED); - /* Get current RX configuration */ + /* Get the current RX configuration. */ v = bus_read_4(sc->sc_res[0], GEM_MAC_RX_CONFIG); /* @@ -2279,7 +2200,7 @@ gem_setladrf(sc) * and hash filter. Depending on the case, the right bit will be * enabled. */ - v &= ~(GEM_MAC_RX_PROMISCUOUS|GEM_MAC_RX_HASH_FILTER| + v &= ~(GEM_MAC_RX_PROMISCUOUS | GEM_MAC_RX_HASH_FILTER | GEM_MAC_RX_PROMISC_GRP); bus_write_4(sc->sc_res[0], GEM_MAC_RX_CONFIG, v); @@ -2298,14 +2219,15 @@ gem_setladrf(sc) } /* - * Set up multicast address filter by passing all multicast addresses - * through a crc generator, and then using the high order 8 bits as an - * index into the 256 bit logical address filter. The high order 4 - * bits selects the word, while the other 4 bits select the bit within - * the word (where bit 0 is the MSB). + * Set up multicast address filter by passing all multicast + * addresses through a crc generator, and then using the high + * order 8 bits as an index into the 256 bit logical address + * filter. The high order 4 bits selects the word, while the + * other 4 bits select the bit within the word (where bit 0 + * is the MSB). */ - /* Clear hash table */ + /* Clear the hash table. */ memset(hash, 0, sizeof(hash)); IF_ADDR_LOCK(ifp); @@ -2315,7 +2237,7 @@ gem_setladrf(sc) crc = ether_crc32_le(LLADDR((struct sockaddr_dl *) inm->ifma_addr), ETHER_ADDR_LEN); - /* Just want the 8 most significant bits. */ + /* We just want the 8 most significant bits. */ crc >>= 24; /* Set the corresponding bit in the filter. */ @@ -2325,13 +2247,12 @@ gem_setladrf(sc) v |= GEM_MAC_RX_HASH_FILTER; - /* Now load the hash table into the chip (if we are using it) */ - for (i = 0; i < 16; i++) { + /* Now load the hash table into the chip (if we are using it). */ + for (i = 0; i < 16; i++) bus_write_4(sc->sc_res[0], - GEM_MAC_HASH0 + i * (GEM_MAC_HASH1-GEM_MAC_HASH0), + GEM_MAC_HASH0 + i * (GEM_MAC_HASH1 - GEM_MAC_HASH0), hash[i]); - } -chipit: + chipit: bus_write_4(sc->sc_res[0], GEM_MAC_RX_CONFIG, v); } diff --git a/sys/dev/gem/if_gem_pci.c b/sys/dev/gem/if_gem_pci.c index 742bf8f4b478..b1bdce3b3d52 100644 --- a/sys/dev/gem/if_gem_pci.c +++ b/sys/dev/gem/if_gem_pci.c @@ -1,5 +1,6 @@ /*- * Copyright (C) 2001 Eduardo Horvath. + * Copyright (c) 2007 Marius Strobl * All rights reserved. * * @@ -63,11 +64,11 @@ __FBSDID("$FreeBSD$"); #include "miibus_if.h" -static int gem_pci_probe(device_t); -static int gem_pci_attach(device_t); -static int gem_pci_detach(device_t); -static int gem_pci_suspend(device_t); -static int gem_pci_resume(device_t); +static int gem_pci_attach(device_t dev); +static int gem_pci_detach(device_t dev); +static int gem_pci_probe(device_t dev); +static int gem_pci_resume(device_t dev); +static int gem_pci_suspend(device_t dev); static device_method_t gem_pci_methods[] = { /* Device interface */ @@ -118,8 +119,7 @@ static const struct gem_pci_dev { }; static int -gem_pci_probe(dev) - device_t dev; +gem_pci_probe(device_t dev) { int i; @@ -140,8 +140,7 @@ static struct resource_spec gem_pci_res_spec[] = { }; static int -gem_pci_attach(dev) - device_t dev; +gem_pci_attach(device_t dev) { struct gem_softc *sc; int i; @@ -166,13 +165,13 @@ gem_pci_attach(dev) /* * Some Sun GEMs/ERIs do have their intpin register bogusly set to 0, - * although it should be 1. correct that. + * although it should be 1. Correct that. */ if (pci_get_intpin(dev) == 0) pci_set_intpin(dev, 1); sc->sc_dev = dev; - sc->sc_flags |= GEM_PCI; /* XXX */ + sc->sc_flags |= GEM_PCI; if (bus_alloc_resources(dev, gem_pci_res_spec, sc->sc_res)) { device_printf(dev, "failed to allocate resources\n"); @@ -225,7 +224,8 @@ gem_pci_attach(dev) /* Read PCI Expansion ROM header. */ if (GEM_ROM_READ_2(sc, PCI_ROMHDR_SIG) != PCI_ROMHDR_SIG_MAGIC || - (i = GEM_ROM_READ_2(sc, PCI_ROMHDR_PTR_DATA)) < PCI_ROMHDR_SIZE) { + (i = GEM_ROM_READ_2(sc, PCI_ROMHDR_PTR_DATA)) < + PCI_ROMHDR_SIZE) { device_printf(dev, "unexpected PCI Expansion ROM header\n"); goto fail; } @@ -234,7 +234,8 @@ gem_pci_attach(dev) if (GEM_ROM_READ_4(sc, i + PCI_ROM_SIG) != PCI_ROM_SIG_MAGIC || GEM_ROM_READ_2(sc, i + PCI_ROM_VENDOR) != pci_get_vendor(dev) || GEM_ROM_READ_2(sc, i + PCI_ROM_DEVICE) != pci_get_device(dev) || - (j = GEM_ROM_READ_2(sc, i + PCI_ROM_PTR_VPD)) < i + PCI_ROM_SIZE) { + (j = GEM_ROM_READ_2(sc, i + PCI_ROM_PTR_VPD)) < + i + PCI_ROM_SIZE) { device_printf(dev, "unexpected PCI Expansion ROM data\n"); goto fail; } @@ -242,14 +243,16 @@ gem_pci_attach(dev) /* * Read PCI VPD. * SUNW,pci-gem cards have a single large resource VPD-R tag - * containing one NA. The VPD used is not in PCI 2.2 standard - * format however. The length in the resource header is in big + * containing one NA. The VPD used is not in PCI 2.2 standard + * format however. The length in the resource header is in big * endian and the end tag is non-standard (0x79) and followed - * by an all-zero "checksum" byte. Sun calls this a "Fresh + * by an all-zero "checksum" byte. Sun calls this a "Fresh * Choice Ethernet" VPD... */ - if (PCI_VPDRES_ISLARGE(GEM_ROM_READ_1(sc, j + PCI_VPDRES_BYTE0)) == 0 || - PCI_VPDRES_LARGE_NAME(GEM_ROM_READ_1(sc, j + PCI_VPDRES_BYTE0)) != + if (PCI_VPDRES_ISLARGE(GEM_ROM_READ_1(sc, + j + PCI_VPDRES_BYTE0)) == 0 || + PCI_VPDRES_LARGE_NAME(GEM_ROM_READ_1(sc, + j + PCI_VPDRES_BYTE0)) != PCI_VPDRES_TYPE_VPD || (GEM_ROM_READ_1(sc, j + PCI_VPDRES_LARGE_LEN_LSB) << 8 | GEM_ROM_READ_1(sc, j + PCI_VPDRES_LARGE_LEN_MSB)) != @@ -270,11 +273,8 @@ gem_pci_attach(dev) ETHER_ADDR_LEN); #endif - /* - * call the main configure - */ if (gem_attach(sc) != 0) { - device_printf(dev, "could not be configured\n"); + device_printf(dev, "could not be attached\n"); goto fail; } @@ -286,18 +286,18 @@ gem_pci_attach(dev) } return (0); -fail: + fail: GEM_LOCK_DESTROY(sc); bus_release_resources(dev, gem_pci_res_spec, sc->sc_res); return (ENXIO); } static int -gem_pci_detach(dev) - device_t dev; +gem_pci_detach(device_t dev) { - struct gem_softc *sc = device_get_softc(dev); + struct gem_softc *sc; + sc = device_get_softc(dev); bus_teardown_intr(dev, sc->sc_res[1], sc->sc_ih); gem_detach(sc); GEM_LOCK_DESTROY(sc); @@ -306,21 +306,21 @@ gem_pci_detach(dev) } static int -gem_pci_suspend(dev) - device_t dev; +gem_pci_suspend(device_t dev) { - struct gem_softc *sc = device_get_softc(dev); + struct gem_softc *sc; + sc = device_get_softc(dev); gem_suspend(sc); return (0); } static int -gem_pci_resume(dev) - device_t dev; +gem_pci_resume(device_t dev) { - struct gem_softc *sc = device_get_softc(dev); + struct gem_softc *sc; + sc = device_get_softc(dev); gem_resume(sc); return (0); } diff --git a/sys/dev/gem/if_gemreg.h b/sys/dev/gem/if_gemreg.h index 4c060c90ea31..569236f96c57 100644 --- a/sys/dev/gem/if_gemreg.h +++ b/sys/dev/gem/if_gemreg.h @@ -37,7 +37,7 @@ #define GEM_SEB_STATE 0x0000 /* SEB state reg, R/O */ #define GEM_CONFIG 0x0004 /* config reg */ #define GEM_STATUS 0x000c /* status reg */ -/* Note: Reading the status reg clears bits 0-6 */ +/* Note: Reading the status reg clears bits 0-6. */ #define GEM_INTMASK 0x0010 #define GEM_INTACK 0x0014 /* Interrupt acknowledge, W/O */ #define GEM_STATUS_ALIAS 0x001c @@ -74,7 +74,7 @@ /* - * Interrupt bits, for both the GEM_STATUS and GEM_INTMASK regs. + * Interrupt bits, for both the GEM_STATUS and GEM_INTMASK regs * Bits 0-6 auto-clear when read. */ #define GEM_INTR_TX_INTME 0x000000001 /* Frame w/INTME bit set sent */ @@ -145,7 +145,7 @@ #define GEM_TX_DEBUG 0x3028 -/* GEM_TX_CONFIG register bits. */ +/* GEM_TX_CONFIG register bits */ #define GEM_TX_CONFIG_TXDMA_EN 0x00000001 /* TX DMA enable */ #define GEM_TX_CONFIG_TXRING_SZ 0x0000001e /* TX ring size */ #define GEM_TX_CONFIG_TXFIFO_TH 0x001ffc00 /* TX fifo threshold */ @@ -194,7 +194,7 @@ #define GEM_RX_FIFO_SIZE 0x4120 -/* GEM_RX_CONFIG register bits. */ +/* GEM_RX_CONFIG register bits */ #define GEM_RX_CONFIG_RXDMA_EN 0x00000001 /* RX DMA enable */ #define GEM_RX_CONFIG_RXRING_SZ 0x0000001e /* RX ring size */ #define GEM_RX_CONFIG_BATCH_DIS 0x00000020 /* desc batching disable */ @@ -361,7 +361,7 @@ #define GEM_MAC_TX_ENABLE 0x00000001 /* TX enable */ #define GEM_MAC_TX_IGN_CARRIER 0x00000002 /* Ignore carrier sense */ #define GEM_MAC_TX_IGN_COLLIS 0x00000004 /* ignore collisions */ -#define GEM_MAC_TX_ENA_IPG0 0x00000008 /* extend Rx-to-TX IPG */ +#define GEM_MAC_TX_ENA_IPG0 0x00000008 /* extend RX-to-TX IPG */ #define GEM_MAC_TX_NGU 0x00000010 /* Never give up */ #define GEM_MAC_TX_NGU_LIMIT 0x00000020 /* Never give up limit */ #define GEM_MAC_TX_NO_BACKOFF 0x00000040 @@ -404,7 +404,7 @@ /* GEM MIF registers */ -/* Bit bang registers use low bit only */ +/* Bit bang registers use low bit only. */ #define GEM_MIF_BB_CLOCK 0x6200 /* bit bang clock */ #define GEM_MIF_BB_DATA 0x6204 /* bit bang data */ #define GEM_MIF_BB_OUTPUT_ENAB 0x6208 @@ -439,7 +439,7 @@ #define GEM_MIF_CONFIG_MDI0 0x00000100 /* MDIO_0 Data/MDIO_0 atached */ #define GEM_MIF_CONFIG_MDI1 0x00000200 /* MDIO_1 Data/MDIO_1 atached */ #define GEM_MIF_CONFIG_PHY_ADR 0x00007c00 /* poll PHY address */ -/* MDI0 is onboard transceiver MDI1 is external, PHYAD for both is 0 */ +/* MDI0 is the onboard transceiver, MDI1 is external, PHYAD for both is 0. */ #define GEM_MIF_CONFIG_BITS "\177\020b\0PHYSEL\0b\1POLL\0b\2BBENA\0" \ "b\x8MDIO0\0b\x9MDIO1\0\0" @@ -455,7 +455,7 @@ */ -/* The GEM PCS/Serial link registers. */ +/* GEM PCS/Serial link registers */ /* DO NOT TOUCH THESE REGISTERS ON ERI -- IT HARD HANGS. */ #define GEM_MII_CONTROL 0x9000 #define GEM_MII_STATUS 0x9004 @@ -583,7 +583,7 @@ #define GEM_PHYAD_EXTERNAL 0 /* - * GEM descriptor table structures. + * GEM descriptor table structures */ struct gem_desc { uint64_t gd_flags; diff --git a/sys/dev/gem/if_gemvar.h b/sys/dev/gem/if_gemvar.h index 08b21051da33..5a2952f95797 100644 --- a/sys/dev/gem/if_gemvar.h +++ b/sys/dev/gem/if_gemvar.h @@ -31,20 +31,15 @@ #ifndef _IF_GEMVAR_H #define _IF_GEMVAR_H - #include #include -/* - * Misc. definitions for the Sun ``Gem'' Ethernet controller family driver. - */ - /* * Transmit descriptor list size. This is arbitrary, but allocate * enough descriptors for 64 pending transmissions and 16 segments - * per packet. This limit is not actually enforced (packets with more segments - * can be sent, depending on the busdma backend); it is however used as an - * estimate for the tx window size. + * per packet. This limit is not actually enforced (packets with + * more segments can be sent, depending on the busdma backend); it + * is however used as an estimate for the TX window size. */ #define GEM_NTXSEGS 16 @@ -55,7 +50,7 @@ #define GEM_NEXTTX(x) ((x + 1) & GEM_NTXDESC_MASK) /* - * Receive descriptor list size. We have one Rx buffer per incoming + * Receive descriptor list size. We have one RX buffer per incoming * packet, so this logic is a little simpler. */ #define GEM_NRXDESC 256 @@ -63,26 +58,19 @@ #define GEM_NEXTRX(x) ((x + 1) & GEM_NRXDESC_MASK) /* - * How many ticks to wait until to retry on a RX descriptor that is still owned - * by the hardware. + * How many ticks to wait until to retry on a RX descriptor that is + * still owned by the hardware. */ #define GEM_RXOWN_TICKS (hz / 50) /* - * Control structures are DMA'd to the GEM chip. We allocate them in - * a single clump that maps to a single DMA segment to make several things - * easier. + * Control structures are DMA'd to the GEM chip. We allocate them + * in a single clump that maps to a single DMA segment to make + * several things easier. */ struct gem_control_data { - /* - * The transmit descriptors. - */ - struct gem_desc gcd_txdescs[GEM_NTXDESC]; - - /* - * The receive descriptors. - */ - struct gem_desc gcd_rxdescs[GEM_NRXDESC]; + struct gem_desc gcd_txdescs[GEM_NTXDESC]; /* TX descriptors */ + struct gem_desc gcd_rxdescs[GEM_NRXDESC]; /* RX descriptors */ }; #define GEM_CDOFF(x) offsetof(struct gem_control_data, x) @@ -90,7 +78,7 @@ struct gem_control_data { #define GEM_CDRXOFF(x) GEM_CDOFF(gcd_rxdescs[(x)]) /* - * Software state for transmit job mbufs (may be elements of mbuf chains). + * software state for transmit job mbufs (may be elements of mbuf chains) */ struct gem_txsoft { struct mbuf *txs_mbuf; /* head of our mbuf chain */ @@ -104,7 +92,7 @@ struct gem_txsoft { STAILQ_HEAD(gem_txsq, gem_txsoft); /* - * Software state for receive jobs. + * software state for receive jobs */ struct gem_rxsoft { struct mbuf *rxs_mbuf; /* head of our mbuf chain */ @@ -113,7 +101,7 @@ struct gem_rxsoft { }; /* - * Software state per device. + * software state per device */ struct gem_softc { struct ifnet *sc_ifp; @@ -123,20 +111,20 @@ struct gem_softc { device_t sc_dev; /* generic device information */ u_char sc_enaddr[ETHER_ADDR_LEN]; struct callout sc_tick_ch; /* tick callout */ - struct callout sc_rx_ch; /* delayed rx callout */ + struct callout sc_rx_ch; /* delayed RX callout */ int sc_wdog_timer; /* watchdog timer */ void *sc_ih; struct resource *sc_res[2]; - bus_dma_tag_t sc_pdmatag; /* parent bus dma tag */ - bus_dma_tag_t sc_rdmatag; /* RX bus dma tag */ - bus_dma_tag_t sc_tdmatag; /* TX bus dma tag */ - bus_dma_tag_t sc_cdmatag; /* control data bus dma tag */ - bus_dmamap_t sc_dmamap; /* bus dma handle */ + bus_dma_tag_t sc_pdmatag; /* parent bus DMA tag */ + bus_dma_tag_t sc_rdmatag; /* RX bus DMA tag */ + bus_dma_tag_t sc_tdmatag; /* TX bus DMA tag */ + bus_dma_tag_t sc_cdmatag; /* control data bus DMA tag */ + bus_dmamap_t sc_dmamap; /* bus DMA handle */ - int sc_phyad; /* addr. of PHY to use or -1 for any */ + int sc_phyad; /* PHY to use or -1 for any */ - u_int sc_variant; /* which GEM are we dealing with? */ + u_int sc_variant; #define GEM_UNKNOWN 0 /* don't know */ #define GEM_SUN_GEM 1 /* Sun GEM */ #define GEM_SUN_ERI 2 /* Sun ERI */ @@ -147,14 +135,14 @@ struct gem_softc { ((sc)->sc_variant == GEM_APPLE_GMAC || \ (sc)->sc_variant == GEM_APPLE_K2_GMAC) - u_int sc_flags; /* */ -#define GEM_INITED (1 << 0) /* reset persistent regs initialized */ + u_int sc_flags; +#define GEM_INITED (1 << 0) /* reset persistent regs init'ed */ #define GEM_LINK (1 << 1) /* link is up */ -#define GEM_PCI (1 << 2) /* XXX PCI busses are little-endian */ +#define GEM_PCI (1 << 2) /* PCI busses are little-endian */ #define GEM_SERDES (1 << 3) /* use the SERDES */ /* - * Ring buffer DMA stuff. + * ring buffer DMA stuff */ bus_dma_segment_t sc_cdseg; /* control data memory */ int sc_cdnseg; /* number of segments */ @@ -162,33 +150,33 @@ struct gem_softc { bus_addr_t sc_cddma; /* - * Software state for transmit and receive descriptors. + * software state for transmit and receive descriptors */ struct gem_txsoft sc_txsoft[GEM_TXQUEUELEN]; struct gem_rxsoft sc_rxsoft[GEM_NRXDESC]; /* - * Control data structures. + * control data structures */ struct gem_control_data *sc_control_data; #define sc_txdescs sc_control_data->gcd_txdescs #define sc_rxdescs sc_control_data->gcd_rxdescs - int sc_txfree; /* number of free Tx descriptors */ - int sc_txnext; /* next ready Tx descriptor */ - int sc_txwin; /* Tx descriptors since last Tx int */ + int sc_txfree; /* number of free TX descriptors */ + int sc_txnext; /* next ready TX descriptor */ + int sc_txwin; /* TX desc. since last TX intr. */ - struct gem_txsq sc_txfreeq; /* free Tx descsofts */ - struct gem_txsq sc_txdirtyq; /* dirty Tx descsofts */ + struct gem_txsq sc_txfreeq; /* free TX descsofts */ + struct gem_txsq sc_txdirtyq; /* dirty TX descsofts */ - int sc_rxptr; /* next ready RX descriptor/descsoft */ - int sc_rxfifosize; /* Rx FIFO size (bytes) */ + int sc_rxptr; /* next ready RX desc./descsoft */ + int sc_rxfifosize; /* RX FIFO size (bytes) */ - /* ========== */ int sc_ifflags; int sc_csum_features; }; +/* XXX this should be handled by bus_dma(9). */ #define GEM_DMA_READ(sc, v) \ ((((sc)->sc_flags & GEM_PCI) != 0) ? le64toh(v) : be64toh(v)) #define GEM_DMA_WRITE(sc, v) \ @@ -237,19 +225,19 @@ do { \ #ifdef _KERNEL extern devclass_t gem_devclass; -int gem_attach(struct gem_softc *); -void gem_detach(struct gem_softc *); -void gem_suspend(struct gem_softc *); -void gem_resume(struct gem_softc *); -void gem_intr(void *); +int gem_attach(struct gem_softc *sc); +void gem_detach(struct gem_softc *sc); +void gem_intr(void *v); +void gem_resume(struct gem_softc *sc); +void gem_suspend(struct gem_softc *sc); -int gem_mediachange(struct ifnet *); -void gem_mediastatus(struct ifnet *, struct ifmediareq *); +int gem_mediachange(struct ifnet *ifp); +void gem_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr); /* MII methods & callbacks */ -int gem_mii_readreg(device_t, int, int); -int gem_mii_writereg(device_t, int, int, int); -void gem_mii_statchg(device_t); +int gem_mii_readreg(device_t dev, int phy, int reg); +void gem_mii_statchg(device_t dev); +int gem_mii_writereg(device_t dev, int phy, int reg, int val); #endif /* _KERNEL */