mirror of
https://github.com/freebsd/freebsd-src
synced 2024-10-15 12:54:27 +00:00
o In preparation for basing a new driver on this one:
- ANSIfy - try to bring closer to style(9) - remove banal comments. o Add my copyright for having done lots of fixes and improvements.
This commit is contained in:
Marius Strobl
parent
d2d9ab366b
commit
2a79fd39b4
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=174987
File diff suppressed because it is too large
Load diff
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@ -1,5 +1,6 @@
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/*-
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* Copyright (C) 2001 Eduardo Horvath.
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* Copyright (c) 2007 Marius Strobl <marius@FreeBSD.org>
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* All rights reserved.
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*
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*
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@ -63,11 +64,11 @@ __FBSDID("$FreeBSD$");
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#include "miibus_if.h"
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static int gem_pci_probe(device_t);
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static int gem_pci_attach(device_t);
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static int gem_pci_detach(device_t);
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static int gem_pci_suspend(device_t);
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static int gem_pci_resume(device_t);
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static int gem_pci_attach(device_t dev);
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static int gem_pci_detach(device_t dev);
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static int gem_pci_probe(device_t dev);
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static int gem_pci_resume(device_t dev);
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static int gem_pci_suspend(device_t dev);
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static device_method_t gem_pci_methods[] = {
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/* Device interface */
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@ -118,8 +119,7 @@ static const struct gem_pci_dev {
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};
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static int
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gem_pci_probe(dev)
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device_t dev;
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gem_pci_probe(device_t dev)
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{
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int i;
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@ -140,8 +140,7 @@ static struct resource_spec gem_pci_res_spec[] = {
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};
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static int
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gem_pci_attach(dev)
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device_t dev;
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gem_pci_attach(device_t dev)
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{
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struct gem_softc *sc;
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int i;
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@ -166,13 +165,13 @@ gem_pci_attach(dev)
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/*
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* Some Sun GEMs/ERIs do have their intpin register bogusly set to 0,
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* although it should be 1. correct that.
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* although it should be 1. Correct that.
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*/
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if (pci_get_intpin(dev) == 0)
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pci_set_intpin(dev, 1);
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sc->sc_dev = dev;
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sc->sc_flags |= GEM_PCI; /* XXX */
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sc->sc_flags |= GEM_PCI;
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if (bus_alloc_resources(dev, gem_pci_res_spec, sc->sc_res)) {
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device_printf(dev, "failed to allocate resources\n");
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@ -225,7 +224,8 @@ gem_pci_attach(dev)
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/* Read PCI Expansion ROM header. */
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if (GEM_ROM_READ_2(sc, PCI_ROMHDR_SIG) != PCI_ROMHDR_SIG_MAGIC ||
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(i = GEM_ROM_READ_2(sc, PCI_ROMHDR_PTR_DATA)) < PCI_ROMHDR_SIZE) {
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(i = GEM_ROM_READ_2(sc, PCI_ROMHDR_PTR_DATA)) <
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PCI_ROMHDR_SIZE) {
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device_printf(dev, "unexpected PCI Expansion ROM header\n");
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goto fail;
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}
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@ -234,7 +234,8 @@ gem_pci_attach(dev)
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if (GEM_ROM_READ_4(sc, i + PCI_ROM_SIG) != PCI_ROM_SIG_MAGIC ||
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GEM_ROM_READ_2(sc, i + PCI_ROM_VENDOR) != pci_get_vendor(dev) ||
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GEM_ROM_READ_2(sc, i + PCI_ROM_DEVICE) != pci_get_device(dev) ||
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(j = GEM_ROM_READ_2(sc, i + PCI_ROM_PTR_VPD)) < i + PCI_ROM_SIZE) {
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(j = GEM_ROM_READ_2(sc, i + PCI_ROM_PTR_VPD)) <
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i + PCI_ROM_SIZE) {
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device_printf(dev, "unexpected PCI Expansion ROM data\n");
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goto fail;
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}
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@ -242,14 +243,16 @@ gem_pci_attach(dev)
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/*
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* Read PCI VPD.
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* SUNW,pci-gem cards have a single large resource VPD-R tag
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* containing one NA. The VPD used is not in PCI 2.2 standard
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* format however. The length in the resource header is in big
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* containing one NA. The VPD used is not in PCI 2.2 standard
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* format however. The length in the resource header is in big
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* endian and the end tag is non-standard (0x79) and followed
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* by an all-zero "checksum" byte. Sun calls this a "Fresh
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* by an all-zero "checksum" byte. Sun calls this a "Fresh
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* Choice Ethernet" VPD...
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*/
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if (PCI_VPDRES_ISLARGE(GEM_ROM_READ_1(sc, j + PCI_VPDRES_BYTE0)) == 0 ||
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PCI_VPDRES_LARGE_NAME(GEM_ROM_READ_1(sc, j + PCI_VPDRES_BYTE0)) !=
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if (PCI_VPDRES_ISLARGE(GEM_ROM_READ_1(sc,
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j + PCI_VPDRES_BYTE0)) == 0 ||
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PCI_VPDRES_LARGE_NAME(GEM_ROM_READ_1(sc,
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j + PCI_VPDRES_BYTE0)) !=
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PCI_VPDRES_TYPE_VPD ||
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(GEM_ROM_READ_1(sc, j + PCI_VPDRES_LARGE_LEN_LSB) << 8 |
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GEM_ROM_READ_1(sc, j + PCI_VPDRES_LARGE_LEN_MSB)) !=
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@ -270,11 +273,8 @@ gem_pci_attach(dev)
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ETHER_ADDR_LEN);
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#endif
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/*
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* call the main configure
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*/
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if (gem_attach(sc) != 0) {
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device_printf(dev, "could not be configured\n");
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device_printf(dev, "could not be attached\n");
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goto fail;
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}
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@ -286,18 +286,18 @@ gem_pci_attach(dev)
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}
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return (0);
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fail:
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fail:
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GEM_LOCK_DESTROY(sc);
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bus_release_resources(dev, gem_pci_res_spec, sc->sc_res);
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return (ENXIO);
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}
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static int
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gem_pci_detach(dev)
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device_t dev;
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gem_pci_detach(device_t dev)
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{
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struct gem_softc *sc = device_get_softc(dev);
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struct gem_softc *sc;
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sc = device_get_softc(dev);
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bus_teardown_intr(dev, sc->sc_res[1], sc->sc_ih);
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gem_detach(sc);
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GEM_LOCK_DESTROY(sc);
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@ -306,21 +306,21 @@ gem_pci_detach(dev)
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}
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static int
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gem_pci_suspend(dev)
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device_t dev;
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gem_pci_suspend(device_t dev)
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{
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struct gem_softc *sc = device_get_softc(dev);
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struct gem_softc *sc;
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sc = device_get_softc(dev);
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gem_suspend(sc);
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return (0);
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}
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static int
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gem_pci_resume(dev)
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device_t dev;
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gem_pci_resume(device_t dev)
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{
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struct gem_softc *sc = device_get_softc(dev);
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struct gem_softc *sc;
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sc = device_get_softc(dev);
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gem_resume(sc);
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return (0);
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}
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@ -37,7 +37,7 @@
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#define GEM_SEB_STATE 0x0000 /* SEB state reg, R/O */
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#define GEM_CONFIG 0x0004 /* config reg */
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#define GEM_STATUS 0x000c /* status reg */
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/* Note: Reading the status reg clears bits 0-6 */
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/* Note: Reading the status reg clears bits 0-6. */
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#define GEM_INTMASK 0x0010
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#define GEM_INTACK 0x0014 /* Interrupt acknowledge, W/O */
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#define GEM_STATUS_ALIAS 0x001c
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@ -74,7 +74,7 @@
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/*
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* Interrupt bits, for both the GEM_STATUS and GEM_INTMASK regs.
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* Interrupt bits, for both the GEM_STATUS and GEM_INTMASK regs
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* Bits 0-6 auto-clear when read.
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*/
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#define GEM_INTR_TX_INTME 0x000000001 /* Frame w/INTME bit set sent */
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@ -145,7 +145,7 @@
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#define GEM_TX_DEBUG 0x3028
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/* GEM_TX_CONFIG register bits. */
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/* GEM_TX_CONFIG register bits */
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#define GEM_TX_CONFIG_TXDMA_EN 0x00000001 /* TX DMA enable */
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#define GEM_TX_CONFIG_TXRING_SZ 0x0000001e /* TX ring size */
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#define GEM_TX_CONFIG_TXFIFO_TH 0x001ffc00 /* TX fifo threshold */
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@ -194,7 +194,7 @@
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#define GEM_RX_FIFO_SIZE 0x4120
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/* GEM_RX_CONFIG register bits. */
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/* GEM_RX_CONFIG register bits */
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#define GEM_RX_CONFIG_RXDMA_EN 0x00000001 /* RX DMA enable */
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#define GEM_RX_CONFIG_RXRING_SZ 0x0000001e /* RX ring size */
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#define GEM_RX_CONFIG_BATCH_DIS 0x00000020 /* desc batching disable */
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@ -361,7 +361,7 @@
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#define GEM_MAC_TX_ENABLE 0x00000001 /* TX enable */
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#define GEM_MAC_TX_IGN_CARRIER 0x00000002 /* Ignore carrier sense */
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#define GEM_MAC_TX_IGN_COLLIS 0x00000004 /* ignore collisions */
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#define GEM_MAC_TX_ENA_IPG0 0x00000008 /* extend Rx-to-TX IPG */
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#define GEM_MAC_TX_ENA_IPG0 0x00000008 /* extend RX-to-TX IPG */
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#define GEM_MAC_TX_NGU 0x00000010 /* Never give up */
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#define GEM_MAC_TX_NGU_LIMIT 0x00000020 /* Never give up limit */
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#define GEM_MAC_TX_NO_BACKOFF 0x00000040
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@ -404,7 +404,7 @@
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/* GEM MIF registers */
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/* Bit bang registers use low bit only */
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/* Bit bang registers use low bit only. */
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#define GEM_MIF_BB_CLOCK 0x6200 /* bit bang clock */
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#define GEM_MIF_BB_DATA 0x6204 /* bit bang data */
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#define GEM_MIF_BB_OUTPUT_ENAB 0x6208
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@ -439,7 +439,7 @@
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#define GEM_MIF_CONFIG_MDI0 0x00000100 /* MDIO_0 Data/MDIO_0 atached */
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#define GEM_MIF_CONFIG_MDI1 0x00000200 /* MDIO_1 Data/MDIO_1 atached */
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#define GEM_MIF_CONFIG_PHY_ADR 0x00007c00 /* poll PHY address */
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/* MDI0 is onboard transceiver MDI1 is external, PHYAD for both is 0 */
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/* MDI0 is the onboard transceiver, MDI1 is external, PHYAD for both is 0. */
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#define GEM_MIF_CONFIG_BITS "\177\020b\0PHYSEL\0b\1POLL\0b\2BBENA\0" \
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"b\x8MDIO0\0b\x9MDIO1\0\0"
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@ -455,7 +455,7 @@
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*/
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/* The GEM PCS/Serial link registers. */
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/* GEM PCS/Serial link registers */
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/* DO NOT TOUCH THESE REGISTERS ON ERI -- IT HARD HANGS. */
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#define GEM_MII_CONTROL 0x9000
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#define GEM_MII_STATUS 0x9004
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@ -583,7 +583,7 @@
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#define GEM_PHYAD_EXTERNAL 0
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/*
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* GEM descriptor table structures.
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* GEM descriptor table structures
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*/
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struct gem_desc {
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uint64_t gd_flags;
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@ -31,20 +31,15 @@
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#ifndef _IF_GEMVAR_H
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#define _IF_GEMVAR_H
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#include <sys/queue.h>
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#include <sys/callout.h>
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/*
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* Misc. definitions for the Sun ``Gem'' Ethernet controller family driver.
|
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*/
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|
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/*
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* Transmit descriptor list size. This is arbitrary, but allocate
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* enough descriptors for 64 pending transmissions and 16 segments
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* per packet. This limit is not actually enforced (packets with more segments
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* can be sent, depending on the busdma backend); it is however used as an
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* estimate for the tx window size.
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* per packet. This limit is not actually enforced (packets with
|
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* more segments can be sent, depending on the busdma backend); it
|
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* is however used as an estimate for the TX window size.
|
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*/
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#define GEM_NTXSEGS 16
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@ -55,7 +50,7 @@
|
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#define GEM_NEXTTX(x) ((x + 1) & GEM_NTXDESC_MASK)
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|
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/*
|
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* Receive descriptor list size. We have one Rx buffer per incoming
|
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* Receive descriptor list size. We have one RX buffer per incoming
|
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* packet, so this logic is a little simpler.
|
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*/
|
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#define GEM_NRXDESC 256
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|
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@ -63,26 +58,19 @@
|
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#define GEM_NEXTRX(x) ((x + 1) & GEM_NRXDESC_MASK)
|
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|
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/*
|
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* How many ticks to wait until to retry on a RX descriptor that is still owned
|
||||
* by the hardware.
|
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* How many ticks to wait until to retry on a RX descriptor that is
|
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* still owned by the hardware.
|
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*/
|
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#define GEM_RXOWN_TICKS (hz / 50)
|
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|
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/*
|
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* Control structures are DMA'd to the GEM chip. We allocate them in
|
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* a single clump that maps to a single DMA segment to make several things
|
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* easier.
|
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* Control structures are DMA'd to the GEM chip. We allocate them
|
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* in a single clump that maps to a single DMA segment to make
|
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* several things easier.
|
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*/
|
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struct gem_control_data {
|
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/*
|
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* The transmit descriptors.
|
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*/
|
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struct gem_desc gcd_txdescs[GEM_NTXDESC];
|
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|
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/*
|
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* The receive descriptors.
|
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*/
|
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struct gem_desc gcd_rxdescs[GEM_NRXDESC];
|
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struct gem_desc gcd_txdescs[GEM_NTXDESC]; /* TX descriptors */
|
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struct gem_desc gcd_rxdescs[GEM_NRXDESC]; /* RX descriptors */
|
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};
|
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|
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#define GEM_CDOFF(x) offsetof(struct gem_control_data, x)
|
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|
|
@ -90,7 +78,7 @@ struct gem_control_data {
|
|||
#define GEM_CDRXOFF(x) GEM_CDOFF(gcd_rxdescs[(x)])
|
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|
||||
/*
|
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* Software state for transmit job mbufs (may be elements of mbuf chains).
|
||||
* software state for transmit job mbufs (may be elements of mbuf chains)
|
||||
*/
|
||||
struct gem_txsoft {
|
||||
struct mbuf *txs_mbuf; /* head of our mbuf chain */
|
||||
|
|
@ -104,7 +92,7 @@ struct gem_txsoft {
|
|||
STAILQ_HEAD(gem_txsq, gem_txsoft);
|
||||
|
||||
/*
|
||||
* Software state for receive jobs.
|
||||
* software state for receive jobs
|
||||
*/
|
||||
struct gem_rxsoft {
|
||||
struct mbuf *rxs_mbuf; /* head of our mbuf chain */
|
||||
|
|
@ -113,7 +101,7 @@ struct gem_rxsoft {
|
|||
};
|
||||
|
||||
/*
|
||||
* Software state per device.
|
||||
* software state per device
|
||||
*/
|
||||
struct gem_softc {
|
||||
struct ifnet *sc_ifp;
|
||||
|
|
@ -123,20 +111,20 @@ struct gem_softc {
|
|||
device_t sc_dev; /* generic device information */
|
||||
u_char sc_enaddr[ETHER_ADDR_LEN];
|
||||
struct callout sc_tick_ch; /* tick callout */
|
||||
struct callout sc_rx_ch; /* delayed rx callout */
|
||||
struct callout sc_rx_ch; /* delayed RX callout */
|
||||
int sc_wdog_timer; /* watchdog timer */
|
||||
|
||||
void *sc_ih;
|
||||
struct resource *sc_res[2];
|
||||
bus_dma_tag_t sc_pdmatag; /* parent bus dma tag */
|
||||
bus_dma_tag_t sc_rdmatag; /* RX bus dma tag */
|
||||
bus_dma_tag_t sc_tdmatag; /* TX bus dma tag */
|
||||
bus_dma_tag_t sc_cdmatag; /* control data bus dma tag */
|
||||
bus_dmamap_t sc_dmamap; /* bus dma handle */
|
||||
bus_dma_tag_t sc_pdmatag; /* parent bus DMA tag */
|
||||
bus_dma_tag_t sc_rdmatag; /* RX bus DMA tag */
|
||||
bus_dma_tag_t sc_tdmatag; /* TX bus DMA tag */
|
||||
bus_dma_tag_t sc_cdmatag; /* control data bus DMA tag */
|
||||
bus_dmamap_t sc_dmamap; /* bus DMA handle */
|
||||
|
||||
int sc_phyad; /* addr. of PHY to use or -1 for any */
|
||||
int sc_phyad; /* PHY to use or -1 for any */
|
||||
|
||||
u_int sc_variant; /* which GEM are we dealing with? */
|
||||
u_int sc_variant;
|
||||
#define GEM_UNKNOWN 0 /* don't know */
|
||||
#define GEM_SUN_GEM 1 /* Sun GEM */
|
||||
#define GEM_SUN_ERI 2 /* Sun ERI */
|
||||
|
|
@ -147,14 +135,14 @@ struct gem_softc {
|
|||
((sc)->sc_variant == GEM_APPLE_GMAC || \
|
||||
(sc)->sc_variant == GEM_APPLE_K2_GMAC)
|
||||
|
||||
u_int sc_flags; /* */
|
||||
#define GEM_INITED (1 << 0) /* reset persistent regs initialized */
|
||||
u_int sc_flags;
|
||||
#define GEM_INITED (1 << 0) /* reset persistent regs init'ed */
|
||||
#define GEM_LINK (1 << 1) /* link is up */
|
||||
#define GEM_PCI (1 << 2) /* XXX PCI busses are little-endian */
|
||||
#define GEM_PCI (1 << 2) /* PCI busses are little-endian */
|
||||
#define GEM_SERDES (1 << 3) /* use the SERDES */
|
||||
|
||||
/*
|
||||
* Ring buffer DMA stuff.
|
||||
* ring buffer DMA stuff
|
||||
*/
|
||||
bus_dma_segment_t sc_cdseg; /* control data memory */
|
||||
int sc_cdnseg; /* number of segments */
|
||||
|
|
@ -162,33 +150,33 @@ struct gem_softc {
|
|||
bus_addr_t sc_cddma;
|
||||
|
||||
/*
|
||||
* Software state for transmit and receive descriptors.
|
||||
* software state for transmit and receive descriptors
|
||||
*/
|
||||
struct gem_txsoft sc_txsoft[GEM_TXQUEUELEN];
|
||||
struct gem_rxsoft sc_rxsoft[GEM_NRXDESC];
|
||||
|
||||
/*
|
||||
* Control data structures.
|
||||
* control data structures
|
||||
*/
|
||||
struct gem_control_data *sc_control_data;
|
||||
#define sc_txdescs sc_control_data->gcd_txdescs
|
||||
#define sc_rxdescs sc_control_data->gcd_rxdescs
|
||||
|
||||
int sc_txfree; /* number of free Tx descriptors */
|
||||
int sc_txnext; /* next ready Tx descriptor */
|
||||
int sc_txwin; /* Tx descriptors since last Tx int */
|
||||
int sc_txfree; /* number of free TX descriptors */
|
||||
int sc_txnext; /* next ready TX descriptor */
|
||||
int sc_txwin; /* TX desc. since last TX intr. */
|
||||
|
||||
struct gem_txsq sc_txfreeq; /* free Tx descsofts */
|
||||
struct gem_txsq sc_txdirtyq; /* dirty Tx descsofts */
|
||||
struct gem_txsq sc_txfreeq; /* free TX descsofts */
|
||||
struct gem_txsq sc_txdirtyq; /* dirty TX descsofts */
|
||||
|
||||
int sc_rxptr; /* next ready RX descriptor/descsoft */
|
||||
int sc_rxfifosize; /* Rx FIFO size (bytes) */
|
||||
int sc_rxptr; /* next ready RX desc./descsoft */
|
||||
int sc_rxfifosize; /* RX FIFO size (bytes) */
|
||||
|
||||
/* ========== */
|
||||
int sc_ifflags;
|
||||
int sc_csum_features;
|
||||
};
|
||||
|
||||
/* XXX this should be handled by bus_dma(9). */
|
||||
#define GEM_DMA_READ(sc, v) \
|
||||
((((sc)->sc_flags & GEM_PCI) != 0) ? le64toh(v) : be64toh(v))
|
||||
#define GEM_DMA_WRITE(sc, v) \
|
||||
|
|
@ -237,19 +225,19 @@ do { \
|
|||
#ifdef _KERNEL
|
||||
extern devclass_t gem_devclass;
|
||||
|
||||
int gem_attach(struct gem_softc *);
|
||||
void gem_detach(struct gem_softc *);
|
||||
void gem_suspend(struct gem_softc *);
|
||||
void gem_resume(struct gem_softc *);
|
||||
void gem_intr(void *);
|
||||
int gem_attach(struct gem_softc *sc);
|
||||
void gem_detach(struct gem_softc *sc);
|
||||
void gem_intr(void *v);
|
||||
void gem_resume(struct gem_softc *sc);
|
||||
void gem_suspend(struct gem_softc *sc);
|
||||
|
||||
int gem_mediachange(struct ifnet *);
|
||||
void gem_mediastatus(struct ifnet *, struct ifmediareq *);
|
||||
int gem_mediachange(struct ifnet *ifp);
|
||||
void gem_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr);
|
||||
|
||||
/* MII methods & callbacks */
|
||||
int gem_mii_readreg(device_t, int, int);
|
||||
int gem_mii_writereg(device_t, int, int, int);
|
||||
void gem_mii_statchg(device_t);
|
||||
int gem_mii_readreg(device_t dev, int phy, int reg);
|
||||
void gem_mii_statchg(device_t dev);
|
||||
int gem_mii_writereg(device_t dev, int phy, int reg, int val);
|
||||
|
||||
#endif /* _KERNEL */
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue