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https://github.com/freebsd/freebsd-src
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Add support for branch instruction on armv7 with ptrace single step
Previous code supported only "continuous" code without any kind of branch instructions. To change that, new function was implemented which parses current instruction and returns an addres where the jump might happen (alternative addr). mdthread structure was extended to support two breakpoints (one directly below current instruction and the second placed at the alternative location). One of them must trigger regardless the instruction has or has not been executed due to condition field. Upon cleanup, both software breakpoints are removed. This implementation parses only the most common instructions that are present in the code (like 99.99% of all), but there is a chance there are some left, not covered by the parsing routine. Parsing is done only for 32-bit instruction, no Thumb nor Thumb-2 support is provided. Reviewed by: kib Submitted by: Wojciech Macek <wma@semihalf.com> Obtained from: Semihalf Sponsored by: Juniper Networks Inc. Differential Revision: https://reviews.freebsd.org/D4021
This commit is contained in:
parent
deeaa1c566
commit
232e189a56
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=290273
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@ -53,6 +53,7 @@ __FBSDID("$FreeBSD$");
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#include <vm/vm_extern.h>
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#include <machine/db_machdep.h>
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#include <machine/machdep.h>
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#include <machine/vmparam.h>
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#include <machine/cpu.h>
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@ -291,94 +292,35 @@ db_fetch_reg(int reg)
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}
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}
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static u_int
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db_branch_taken_read_int(void *cookie __unused, vm_offset_t offset, u_int *val)
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{
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u_int ret;
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db_read_bytes(offset, 4, (char *)&ret);
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*val = ret;
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return (0);
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}
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static u_int
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db_branch_taken_fetch_reg(void *cookie __unused, int reg)
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{
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return (db_fetch_reg(reg));
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}
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u_int
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branch_taken(u_int insn, db_addr_t pc)
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{
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u_int addr, nregs, offset = 0;
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register_t new_pc;
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int ret;
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switch ((insn >> 24) & 0xf) {
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case 0x2: /* add pc, reg1, #value */
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case 0x0: /* add pc, reg1, reg2, lsl #offset */
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addr = db_fetch_reg((insn >> 16) & 0xf);
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if (((insn >> 16) & 0xf) == 15)
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addr += 8;
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if (insn & 0x0200000) {
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offset = (insn >> 7) & 0x1e;
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offset = (insn & 0xff) << (32 - offset) |
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(insn & 0xff) >> offset;
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} else {
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ret = arm_predict_branch(NULL, insn, (register_t)pc, &new_pc,
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db_branch_taken_fetch_reg, db_branch_taken_read_int);
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offset = db_fetch_reg(insn & 0x0f);
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if ((insn & 0x0000ff0) != 0x00000000) {
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if (insn & 0x10)
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nregs = db_fetch_reg((insn >> 8) & 0xf);
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else
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nregs = (insn >> 7) & 0x1f;
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switch ((insn >> 5) & 3) {
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case 0:
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/* lsl */
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offset = offset << nregs;
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break;
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case 1:
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/* lsr */
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offset = offset >> nregs;
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break;
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default:
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break; /* XXX */
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}
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}
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return (addr + offset);
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}
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case 0xa: /* b ... */
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case 0xb: /* bl ... */
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addr = ((insn << 2) & 0x03ffffff);
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if (addr & 0x02000000)
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addr |= 0xfc000000;
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return (pc + 8 + addr);
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case 0x7: /* ldr pc, [pc, reg, lsl #2] */
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addr = db_fetch_reg(insn & 0xf);
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addr = pc + 8 + (addr << 2);
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db_read_bytes(addr, 4, (char *)&addr);
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return (addr);
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case 0x1: /* mov pc, reg */
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addr = db_fetch_reg(insn & 0xf);
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return (addr);
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case 0x4:
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case 0x5: /* ldr pc, [reg] */
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addr = db_fetch_reg((insn >> 16) & 0xf);
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/* ldr pc, [reg, #offset] */
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if (insn & (1 << 24))
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offset = insn & 0xfff;
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if (insn & 0x00800000)
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addr += offset;
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else
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addr -= offset;
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db_read_bytes(addr, 4, (char *)&addr);
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return (addr);
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case 0x8: /* ldmxx reg, {..., pc} */
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case 0x9:
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addr = db_fetch_reg((insn >> 16) & 0xf);
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nregs = (insn & 0x5555) + ((insn >> 1) & 0x5555);
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nregs = (nregs & 0x3333) + ((nregs >> 2) & 0x3333);
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nregs = (nregs + (nregs >> 4)) & 0x0f0f;
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nregs = (nregs + (nregs >> 8)) & 0x001f;
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switch ((insn >> 23) & 0x3) {
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case 0x0: /* ldmda */
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addr = addr - 0;
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break;
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case 0x1: /* ldmia */
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addr = addr + 0 + ((nregs - 1) << 2);
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break;
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case 0x2: /* ldmdb */
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addr = addr - 4;
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break;
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case 0x3: /* ldmib */
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addr = addr + 4 + ((nregs - 1) << 2);
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break;
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}
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db_read_bytes(addr, 4, (char *)&addr);
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return (addr);
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default:
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panic("branch_taken: botch");
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}
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if (ret != 0)
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kdb_reenter();
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return (new_pc);
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}
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@ -95,6 +95,7 @@ __FBSDID("$FreeBSD$");
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#include <machine/atags.h>
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#include <machine/cpu.h>
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#include <machine/cpuinfo.h>
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#include <machine/db_machdep.h>
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#include <machine/devmap.h>
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#include <machine/frame.h>
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#include <machine/intr.h>
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@ -627,11 +628,81 @@ ptrace_write_int(struct thread *td, vm_offset_t addr, u_int32_t v)
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return proc_rwmem(td->td_proc, &uio);
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}
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static u_int
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ptrace_get_usr_reg(void *cookie, int reg)
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{
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int ret;
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struct thread *td = cookie;
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KASSERT(((reg >= 0) && (reg <= ARM_REG_NUM_PC)),
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("reg is outside range"));
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switch(reg) {
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case ARM_REG_NUM_PC:
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ret = td->td_frame->tf_pc;
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break;
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case ARM_REG_NUM_LR:
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ret = td->td_frame->tf_usr_lr;
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break;
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case ARM_REG_NUM_SP:
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ret = td->td_frame->tf_usr_sp;
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break;
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default:
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ret = *((register_t*)&td->td_frame->tf_r0 + reg);
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break;
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}
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return (ret);
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}
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static u_int
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ptrace_get_usr_int(void* cookie, vm_offset_t offset, u_int* val)
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{
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struct thread *td = cookie;
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u_int error;
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error = ptrace_read_int(td, offset, val);
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return (error);
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}
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/**
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* This function parses current instruction opcode and decodes
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* any possible jump (change in PC) which might occur after
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* the instruction is executed.
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*
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* @param td Thread structure of analysed task
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* @param cur_instr Currently executed instruction
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* @param alt_next_address Pointer to the variable where
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* the destination address of the
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* jump instruction shall be stored.
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*
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* @return <0> when jump is possible
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* <EINVAL> otherwise
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*/
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static int
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ptrace_get_alternative_next(struct thread *td, uint32_t cur_instr,
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uint32_t *alt_next_address)
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{
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int error;
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if (inst_branch(cur_instr) || inst_call(cur_instr) ||
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inst_return(cur_instr)) {
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error = arm_predict_branch(td, cur_instr, td->td_frame->tf_pc,
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alt_next_address, ptrace_get_usr_reg, ptrace_get_usr_int);
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return (error);
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}
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return (EINVAL);
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}
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int
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ptrace_single_step(struct thread *td)
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{
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struct proc *p;
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int error;
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int error, error_alt;
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uint32_t cur_instr, alt_next = 0;
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/* TODO: This needs to be updated for Thumb-2 */
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if ((td->td_frame->tf_spsr & PSR_T) != 0)
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@ -639,20 +710,48 @@ ptrace_single_step(struct thread *td)
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KASSERT(td->td_md.md_ptrace_instr == 0,
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("Didn't clear single step"));
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KASSERT(td->td_md.md_ptrace_instr_alt == 0,
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("Didn't clear alternative single step"));
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p = td->td_proc;
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PROC_UNLOCK(p);
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error = ptrace_read_int(td, td->td_frame->tf_pc + 4,
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&td->td_md.md_ptrace_instr);
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error = ptrace_read_int(td, td->td_frame->tf_pc,
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&cur_instr);
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if (error)
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goto out;
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error = ptrace_write_int(td, td->td_frame->tf_pc + 4,
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PTRACE_BREAKPOINT);
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if (error)
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td->td_md.md_ptrace_instr = 0;
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td->td_md.md_ptrace_addr = td->td_frame->tf_pc + 4;
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error = ptrace_read_int(td, td->td_frame->tf_pc + INSN_SIZE,
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&td->td_md.md_ptrace_instr);
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if (error == 0) {
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error = ptrace_write_int(td, td->td_frame->tf_pc + INSN_SIZE,
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PTRACE_BREAKPOINT);
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if (error) {
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td->td_md.md_ptrace_instr = 0;
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} else {
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td->td_md.md_ptrace_addr = td->td_frame->tf_pc +
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INSN_SIZE;
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}
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}
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error_alt = ptrace_get_alternative_next(td, cur_instr, &alt_next);
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if (error_alt == 0) {
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error_alt = ptrace_read_int(td, alt_next,
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&td->td_md.md_ptrace_instr_alt);
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if (error_alt) {
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td->td_md.md_ptrace_instr_alt = 0;
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} else {
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error_alt = ptrace_write_int(td, alt_next,
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PTRACE_BREAKPOINT);
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if (error_alt)
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td->td_md.md_ptrace_instr_alt = 0;
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else
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td->td_md.md_ptrace_addr_alt = alt_next;
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}
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}
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out:
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PROC_LOCK(p);
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return (error);
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return ((error != 0) && (error_alt != 0));
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}
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int
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@ -664,7 +763,7 @@ ptrace_clear_single_step(struct thread *td)
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if ((td->td_frame->tf_spsr & PSR_T) != 0)
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return (EINVAL);
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if (td->td_md.md_ptrace_instr) {
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if (td->td_md.md_ptrace_instr != 0) {
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p = td->td_proc;
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PROC_UNLOCK(p);
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ptrace_write_int(td, td->td_md.md_ptrace_addr,
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@ -672,6 +771,16 @@ ptrace_clear_single_step(struct thread *td)
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PROC_LOCK(p);
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td->td_md.md_ptrace_instr = 0;
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}
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if (td->td_md.md_ptrace_instr_alt != 0) {
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p = td->td_proc;
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PROC_UNLOCK(p);
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ptrace_write_int(td, td->td_md.md_ptrace_addr_alt,
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td->td_md.md_ptrace_instr_alt);
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PROC_LOCK(p);
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td->td_md.md_ptrace_instr_alt = 0;
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}
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return (0);
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}
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@ -1074,6 +1183,111 @@ init_proc0(vm_offset_t kstack)
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pcpup->pc_curpcb = thread0.td_pcb;
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}
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int
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arm_predict_branch(void *cookie, u_int insn, register_t pc, register_t *new_pc,
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u_int (*fetch_reg)(void*, int), u_int (*read_int)(void*, vm_offset_t, u_int*))
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{
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u_int addr, nregs, offset = 0;
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int error = 0;
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switch ((insn >> 24) & 0xf) {
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case 0x2: /* add pc, reg1, #value */
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case 0x0: /* add pc, reg1, reg2, lsl #offset */
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addr = fetch_reg(cookie, (insn >> 16) & 0xf);
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if (((insn >> 16) & 0xf) == 15)
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addr += 8;
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if (insn & 0x0200000) {
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offset = (insn >> 7) & 0x1e;
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offset = (insn & 0xff) << (32 - offset) |
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(insn & 0xff) >> offset;
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} else {
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offset = fetch_reg(cookie, insn & 0x0f);
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if ((insn & 0x0000ff0) != 0x00000000) {
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if (insn & 0x10)
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nregs = fetch_reg(cookie,
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(insn >> 8) & 0xf);
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else
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nregs = (insn >> 7) & 0x1f;
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switch ((insn >> 5) & 3) {
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case 0:
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/* lsl */
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offset = offset << nregs;
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break;
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case 1:
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/* lsr */
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offset = offset >> nregs;
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break;
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default:
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break; /* XXX */
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}
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}
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*new_pc = addr + offset;
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return (0);
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}
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case 0xa: /* b ... */
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case 0xb: /* bl ... */
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addr = ((insn << 2) & 0x03ffffff);
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if (addr & 0x02000000)
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addr |= 0xfc000000;
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*new_pc = (pc + 8 + addr);
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return (0);
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case 0x7: /* ldr pc, [pc, reg, lsl #2] */
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addr = fetch_reg(cookie, insn & 0xf);
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addr = pc + 8 + (addr << 2);
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error = read_int(cookie, addr, &addr);
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*new_pc = addr;
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return (error);
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case 0x1: /* mov pc, reg */
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*new_pc = fetch_reg(cookie, insn & 0xf);
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return (0);
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case 0x4:
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case 0x5: /* ldr pc, [reg] */
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addr = fetch_reg(cookie, (insn >> 16) & 0xf);
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/* ldr pc, [reg, #offset] */
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if (insn & (1 << 24))
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offset = insn & 0xfff;
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if (insn & 0x00800000)
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addr += offset;
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else
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addr -= offset;
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error = read_int(cookie, addr, &addr);
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*new_pc = addr;
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return (error);
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case 0x8: /* ldmxx reg, {..., pc} */
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case 0x9:
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addr = fetch_reg(cookie, (insn >> 16) & 0xf);
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nregs = (insn & 0x5555) + ((insn >> 1) & 0x5555);
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nregs = (nregs & 0x3333) + ((nregs >> 2) & 0x3333);
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nregs = (nregs + (nregs >> 4)) & 0x0f0f;
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nregs = (nregs + (nregs >> 8)) & 0x001f;
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switch ((insn >> 23) & 0x3) {
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case 0x0: /* ldmda */
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addr = addr - 0;
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break;
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case 0x1: /* ldmia */
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addr = addr + 0 + ((nregs - 1) << 2);
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break;
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case 0x2: /* ldmdb */
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addr = addr - 4;
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break;
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case 0x3: /* ldmib */
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addr = addr + 4 + ((nregs - 1) << 2);
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break;
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}
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error = read_int(cookie, addr, &addr);
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*new_pc = addr;
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return (error);
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default:
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return (EINVAL);
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}
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}
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#ifdef ARM_NEW_PMAP
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void
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set_stackptrs(int cpu)
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@ -444,6 +444,12 @@
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#define INSN_COND_MASK 0xf0000000 /* Condition mask */
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#define INSN_COND_AL 0xe0000000 /* Always condition */
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/* ARM register defines */
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#define ARM_REG_SIZE 4
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#define ARM_REG_NUM_PC 15
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#define ARM_REG_NUM_LR 14
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#define ARM_REG_NUM_SP 13
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#define THUMB_INSN_SIZE 2 /* Some are 4 bytes. */
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#endif /* !MACHINE_ARMREG_H */
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@ -74,7 +74,7 @@ typedef int db_expr_t;
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#define inst_branch(ins) (((ins) & 0x0f000000) == 0x0a000000 || \
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((ins) & 0x0fdffff0) == 0x079ff100 || \
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((ins) & 0x0cf0f000) == 0x0490f000 || \
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((ins) & 0x0cd0f000) == 0x0490f000 || \
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((ins) & 0x0ffffff0) == 0x012fff30 || /* blx */ \
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((ins) & 0x0de0f000) == 0x0080f000)
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@ -90,7 +90,7 @@ typedef int db_expr_t;
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int db_validate_address(vm_offset_t);
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u_int branch_taken (u_int insn, u_int pc);
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u_int branch_taken (u_int insn, db_addr_t pc);
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#ifdef __ARMEB__
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#define BYTE_MSF (1)
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@ -43,4 +43,7 @@ void arm_generic_initclocks(void);
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void board_set_serial(uint64_t);
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void board_set_revision(uint32_t);
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||||
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int arm_predict_branch(void *, u_int, register_t, register_t *,
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||||
u_int (*)(void*, int), u_int (*)(void*, vm_offset_t, u_int*));
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||||
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||||
#endif /* !_MACHINE_MACHDEP_H_ */
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||||
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@ -51,6 +51,8 @@ struct mdthread {
|
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register_t md_spurflt_addr; /* (k) Spurious page fault address. */
|
||||
int md_ptrace_instr;
|
||||
int md_ptrace_addr;
|
||||
int md_ptrace_instr_alt;
|
||||
int md_ptrace_addr_alt;
|
||||
register_t md_tp;
|
||||
void *md_ras_start;
|
||||
void *md_ras_end;
|
||||
|
|
Loading…
Reference in a new issue