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Flush the fifos at the correct place in cyopen(). Various things
in cyopen() were done in a different order than in sioopen(), partly to (ab)use a side effect of comparam() and partly because I didn't understand what the reset was doing (it flushes the fifos). This turned out to be more than a cosmetic problem. Flushing the fifos quite late is good for discarding input that arrived while the line state was being initialized, and in the cy driver it also seems to reduce a problem with input that arrived long ago during the previous close (the UART loses sync too easily and for too long).
This commit is contained in:
Bruce Evans
parent
6f93bf5f4b
commit
223f865ada
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=42045
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@ -27,7 +27,7 @@
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $Id: cy.c,v 1.80 1998/12/17 19:23:09 bde Exp $
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* $Id: cy.c,v 1.81 1998/12/19 16:28:57 bde Exp $
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*/
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#include "opt_compat.h"
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@ -37,7 +37,6 @@
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/*
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* TODO:
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* Fix overflows when closing line.
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* Atomic COR change.
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* Consoles.
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*/
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@ -745,45 +744,25 @@ sioopen(dev, flag, mode, p)
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tp->t_ififosize = 2 * RS_IBUFSIZE;
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tp->t_ispeedwat = (speed_t)-1;
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tp->t_ospeedwat = (speed_t)-1;
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#if 0
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(void)commctl(com, TIOCM_DTR | TIOCM_RTS, DMSET);
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com->poll = com->no_irq;
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com->poll_output = com->loses_outints;
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#endif
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++com->wopeners;
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/* reset this channel */
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cd1400_channel_cmd(com, CD1400_CCR_CMDRESET);
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/*
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* Resetting disables the transmitter and receiver as well as
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* flushing the fifos so some of our cached state becomes
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* invalid. The documentation suggests that all registers
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* for the current channel are reset to defaults, but
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* apparently none are. We wouldn't want DTR cleared.
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*/
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com->channel_control = 0;
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/* Encode per-board unit in LIVR for access in intr routines. */
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cd_setreg(com, CD1400_LIVR,
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(unit & CD1400_xIVR_CHAN) << CD1400_xIVR_CHAN_SHIFT);
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/*
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* raise dtr and generally set things up correctly. this
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* has the side-effect of selecting the appropriate cd1400
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* channel, to help us with subsequent channel control stuff
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*/
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(void)commctl(com, TIOCM_DTR | TIOCM_RTS, DMSET);
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#if 0
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com->poll = com->no_irq;
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com->poll_output = com->loses_outints;
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#endif
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++com->wopeners;
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error = comparam(tp, &tp->t_termios);
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--com->wopeners;
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if (error != 0)
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goto out;
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/*
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* XXX we should goto open_top if comparam() slept.
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*/
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#if 0
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if (com->hasfifo) {
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/*
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* (Re)enable and drain fifos.
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* (Re)enable and flush fifos.
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*
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* Certain SMC chips cause problems if the fifos
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* are enabled while input is ready. Turn off the
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@ -815,8 +794,15 @@ sioopen(dev, flag, mode, p)
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| IER_EMSC);
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enable_intr();
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#else /* !0 */
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/* XXX raise RTS too */
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(void)commctl(com, TIOCM_DTR | TIOCM_RTS, DMSET);
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/*
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* Flush fifos. This requires a full channel reset which
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* also disables the transmitter and receiver. Recover
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* from this.
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*/
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cd1400_channel_cmd(com,
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CD1400_CCR_CMDRESET | CD1400_CCR_CHANRESET);
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cd1400_channel_cmd(com, com->channel_control);
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disable_intr();
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com->prev_modem_status = com->last_modem_status
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= cd_getreg(com, CD1400_MSVR2);
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@ -27,7 +27,7 @@
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $Id: cy.c,v 1.80 1998/12/17 19:23:09 bde Exp $
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* $Id: cy.c,v 1.81 1998/12/19 16:28:57 bde Exp $
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*/
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#include "opt_compat.h"
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@ -37,7 +37,6 @@
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/*
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* TODO:
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* Fix overflows when closing line.
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* Atomic COR change.
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* Consoles.
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*/
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@ -745,45 +744,25 @@ sioopen(dev, flag, mode, p)
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tp->t_ififosize = 2 * RS_IBUFSIZE;
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tp->t_ispeedwat = (speed_t)-1;
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tp->t_ospeedwat = (speed_t)-1;
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#if 0
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(void)commctl(com, TIOCM_DTR | TIOCM_RTS, DMSET);
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com->poll = com->no_irq;
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com->poll_output = com->loses_outints;
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#endif
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++com->wopeners;
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/* reset this channel */
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cd1400_channel_cmd(com, CD1400_CCR_CMDRESET);
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/*
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* Resetting disables the transmitter and receiver as well as
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* flushing the fifos so some of our cached state becomes
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* invalid. The documentation suggests that all registers
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* for the current channel are reset to defaults, but
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* apparently none are. We wouldn't want DTR cleared.
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*/
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com->channel_control = 0;
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/* Encode per-board unit in LIVR for access in intr routines. */
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cd_setreg(com, CD1400_LIVR,
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(unit & CD1400_xIVR_CHAN) << CD1400_xIVR_CHAN_SHIFT);
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/*
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* raise dtr and generally set things up correctly. this
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* has the side-effect of selecting the appropriate cd1400
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* channel, to help us with subsequent channel control stuff
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*/
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(void)commctl(com, TIOCM_DTR | TIOCM_RTS, DMSET);
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#if 0
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com->poll = com->no_irq;
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com->poll_output = com->loses_outints;
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#endif
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++com->wopeners;
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error = comparam(tp, &tp->t_termios);
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--com->wopeners;
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if (error != 0)
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goto out;
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/*
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* XXX we should goto open_top if comparam() slept.
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*/
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#if 0
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if (com->hasfifo) {
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/*
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* (Re)enable and drain fifos.
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* (Re)enable and flush fifos.
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*
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* Certain SMC chips cause problems if the fifos
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* are enabled while input is ready. Turn off the
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@ -815,8 +794,15 @@ sioopen(dev, flag, mode, p)
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| IER_EMSC);
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enable_intr();
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#else /* !0 */
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/* XXX raise RTS too */
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(void)commctl(com, TIOCM_DTR | TIOCM_RTS, DMSET);
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/*
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* Flush fifos. This requires a full channel reset which
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* also disables the transmitter and receiver. Recover
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* from this.
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*/
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cd1400_channel_cmd(com,
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CD1400_CCR_CMDRESET | CD1400_CCR_CHANRESET);
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cd1400_channel_cmd(com, com->channel_control);
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disable_intr();
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com->prev_modem_status = com->last_modem_status
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= cd_getreg(com, CD1400_MSVR2);
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@ -27,7 +27,7 @@
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $Id: cy.c,v 1.80 1998/12/17 19:23:09 bde Exp $
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* $Id: cy.c,v 1.81 1998/12/19 16:28:57 bde Exp $
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*/
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#include "opt_compat.h"
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@ -37,7 +37,6 @@
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/*
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* TODO:
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* Fix overflows when closing line.
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* Atomic COR change.
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* Consoles.
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*/
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@ -745,45 +744,25 @@ sioopen(dev, flag, mode, p)
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tp->t_ififosize = 2 * RS_IBUFSIZE;
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tp->t_ispeedwat = (speed_t)-1;
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tp->t_ospeedwat = (speed_t)-1;
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#if 0
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(void)commctl(com, TIOCM_DTR | TIOCM_RTS, DMSET);
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com->poll = com->no_irq;
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com->poll_output = com->loses_outints;
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#endif
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++com->wopeners;
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/* reset this channel */
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cd1400_channel_cmd(com, CD1400_CCR_CMDRESET);
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/*
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* Resetting disables the transmitter and receiver as well as
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* flushing the fifos so some of our cached state becomes
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* invalid. The documentation suggests that all registers
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* for the current channel are reset to defaults, but
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* apparently none are. We wouldn't want DTR cleared.
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*/
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com->channel_control = 0;
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/* Encode per-board unit in LIVR for access in intr routines. */
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cd_setreg(com, CD1400_LIVR,
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(unit & CD1400_xIVR_CHAN) << CD1400_xIVR_CHAN_SHIFT);
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/*
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* raise dtr and generally set things up correctly. this
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* has the side-effect of selecting the appropriate cd1400
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* channel, to help us with subsequent channel control stuff
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*/
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(void)commctl(com, TIOCM_DTR | TIOCM_RTS, DMSET);
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#if 0
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com->poll = com->no_irq;
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com->poll_output = com->loses_outints;
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#endif
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++com->wopeners;
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error = comparam(tp, &tp->t_termios);
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--com->wopeners;
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if (error != 0)
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goto out;
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/*
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* XXX we should goto open_top if comparam() slept.
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*/
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#if 0
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if (com->hasfifo) {
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/*
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* (Re)enable and drain fifos.
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* (Re)enable and flush fifos.
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*
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* Certain SMC chips cause problems if the fifos
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* are enabled while input is ready. Turn off the
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@ -815,8 +794,15 @@ sioopen(dev, flag, mode, p)
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| IER_EMSC);
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enable_intr();
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#else /* !0 */
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/* XXX raise RTS too */
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(void)commctl(com, TIOCM_DTR | TIOCM_RTS, DMSET);
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/*
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* Flush fifos. This requires a full channel reset which
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* also disables the transmitter and receiver. Recover
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* from this.
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*/
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cd1400_channel_cmd(com,
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CD1400_CCR_CMDRESET | CD1400_CCR_CHANRESET);
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cd1400_channel_cmd(com, com->channel_control);
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disable_intr();
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com->prev_modem_status = com->last_modem_status
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= cd_getreg(com, CD1400_MSVR2);
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