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Re-order the TRs so that there're less gaps. This could have a performance

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impact.
This commit is contained in:
Marcel Moolenaar 2011-03-15 06:07:02 +00:00
parent ebad0c04a2
commit 2133803023
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/projects/altix/; revision=219658
1 changed files with 5 additions and 5 deletions
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10
sys/ia64/ia64/machdep.c
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@ -636,7 +636,7 @@ map_vhpt(uintptr_t vhpt)
ia64_set_ifa(vhpt);
ia64_set_itir(pmap_vhpt_log2size << 2);
ia64_srlz_d();
__asm __volatile("itr.d dtr[%0]=%1" :: "r"(2), "r"(pte));
__asm __volatile("itr.d dtr[%0]=%1" :: "r"(4), "r"(pte));
__asm __volatile("mov psr.l=%0" :: "r" (psr));
ia64_srlz_i();
}
@ -674,9 +674,9 @@ map_pal_code(void)
ia64_set_ifa(va);
ia64_set_itir(shft << 2);
ia64_srlz_d();
__asm __volatile("itr.d dtr[%0]=%1" :: "r"(3), "r"(pte));
__asm __volatile("itr.d dtr[%0]=%1" :: "r"(2), "r"(pte));
ia64_srlz_d();
__asm __volatile("itr.i itr[%0]=%1" :: "r"(3), "r"(pte));
__asm __volatile("itr.i itr[%0]=%1" :: "r"(2), "r"(pte));
__asm __volatile("mov psr.l=%0" :: "r" (psr));
ia64_srlz_i();
}
@ -700,9 +700,9 @@ map_gateway_page(void)
ia64_set_ifa(VM_MAXUSER_ADDRESS);
ia64_set_itir(PAGE_SHIFT << 2);
ia64_srlz_d();
__asm __volatile("itr.d dtr[%0]=%1" :: "r"(4), "r"(pte));
__asm __volatile("itr.d dtr[%0]=%1" :: "r"(3), "r"(pte));
ia64_srlz_d();
__asm __volatile("itr.i itr[%0]=%1" :: "r"(4), "r"(pte));
__asm __volatile("itr.i itr[%0]=%1" :: "r"(3), "r"(pte));
__asm __volatile("mov psr.l=%0" :: "r" (psr));
ia64_srlz_i();