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Re-order the TRs so that there're less gaps. This could have a performance
impact.
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parent
ebad0c04a2
commit
2133803023
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/projects/altix/; revision=219658
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@ -636,7 +636,7 @@ map_vhpt(uintptr_t vhpt)
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ia64_set_ifa(vhpt);
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ia64_set_itir(pmap_vhpt_log2size << 2);
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ia64_srlz_d();
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__asm __volatile("itr.d dtr[%0]=%1" :: "r"(2), "r"(pte));
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__asm __volatile("itr.d dtr[%0]=%1" :: "r"(4), "r"(pte));
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__asm __volatile("mov psr.l=%0" :: "r" (psr));
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ia64_srlz_i();
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}
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@ -674,9 +674,9 @@ map_pal_code(void)
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ia64_set_ifa(va);
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ia64_set_itir(shft << 2);
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ia64_srlz_d();
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__asm __volatile("itr.d dtr[%0]=%1" :: "r"(3), "r"(pte));
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__asm __volatile("itr.d dtr[%0]=%1" :: "r"(2), "r"(pte));
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ia64_srlz_d();
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__asm __volatile("itr.i itr[%0]=%1" :: "r"(3), "r"(pte));
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__asm __volatile("itr.i itr[%0]=%1" :: "r"(2), "r"(pte));
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__asm __volatile("mov psr.l=%0" :: "r" (psr));
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ia64_srlz_i();
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}
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@ -700,9 +700,9 @@ map_gateway_page(void)
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ia64_set_ifa(VM_MAXUSER_ADDRESS);
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ia64_set_itir(PAGE_SHIFT << 2);
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ia64_srlz_d();
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__asm __volatile("itr.d dtr[%0]=%1" :: "r"(4), "r"(pte));
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__asm __volatile("itr.d dtr[%0]=%1" :: "r"(3), "r"(pte));
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ia64_srlz_d();
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__asm __volatile("itr.i itr[%0]=%1" :: "r"(4), "r"(pte));
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__asm __volatile("itr.i itr[%0]=%1" :: "r"(3), "r"(pte));
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__asm __volatile("mov psr.l=%0" :: "r" (psr));
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ia64_srlz_i();
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