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Fix PCIe hardware swap configuration for Netlogic XLP

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The last 12 bits of the limit registers have to be set to 1. These
bits are not significant in bridge BARs and are 0 on read, but the
bits are valid in the swap limit register and needs to be set.
This commit is contained in:
Jayachandran C. 2012-07-09 10:17:06 +00:00
parent 2ef23c6d3b
commit 21221d1f6b
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=238289
1 changed files with 2 additions and 2 deletions
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4
sys/mips/nlm/xlp_pci.c
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@ -507,13 +507,13 @@ xlp_pcib_hardware_swap_enable(int node, int link)
nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_MEM_BASE, bar);
bar = nlm_read_bridge_reg(bbase, BRIDGE_PCIEMEM_LIMIT0 + link);
nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_MEM_LIM, bar);
nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_MEM_LIM, bar | 0xFFF);
bar = nlm_read_bridge_reg(bbase, BRIDGE_PCIEIO_BASE0 + link);
nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_IO_BASE, bar);
bar = nlm_read_bridge_reg(bbase, BRIDGE_PCIEIO_LIMIT0 + link);
nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_IO_LIM, bar);
nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_IO_LIM, bar | 0xFFF);
}
static int