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add TBTT interrupt support; this was added in Griffin so consumers should

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check HAL_CAP_INTRMASK before using it

NB: didn't test 11n parts yet so supported only for 5212-class parts
This commit is contained in:
Sam Leffler 2009-05-19 17:53:53 +00:00
parent 00e602a997
commit 210411e0f1
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=192400
4 changed files with 15 additions and 5 deletions
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4
sys/dev/ath/ath_hal/ah.h
View file

@ -335,6 +335,7 @@ typedef enum {
HAL_INT_GPIO = 0x01000000,
HAL_INT_CABEND = 0x02000000, /* Non-common mapping */
HAL_INT_TSFOOR = 0x04000000, /* Non-common mapping */
HAL_INT_TBTT = 0x08000000, /* Non-common mapping */
HAL_INT_CST = 0x10000000, /* Non-common mapping */
HAL_INT_GTT = 0x20000000, /* Non-common mapping */
HAL_INT_FATAL = 0x40000000, /* Non-common mapping */
@ -342,7 +343,8 @@ typedef enum {
HAL_INT_BMISC = HAL_INT_TIM
| HAL_INT_DTIM
| HAL_INT_DTIMSYNC
| HAL_INT_CABEND,
| HAL_INT_CABEND
| HAL_INT_TBTT,
/* Interrupt bits that map directly to ISR/IMR bits */
HAL_INT_COMMON = HAL_INT_RXNOFRM

2
sys/dev/ath/ath_hal/ar5212/ar5212_attach.c
View file

@ -847,6 +847,8 @@ ar5212FillCapabilityInfo(struct ath_hal *ah)
| HAL_INT_BNR
| HAL_INT_BMISC
;
if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_GRIFFIN)
pCap->halIntrMask &= ~HAL_INT_TBTT;
return AH_TRUE;
#undef IS_COBRA

4
sys/dev/ath/ath_hal/ar5212/ar5212_interrupts.c
View file

@ -70,6 +70,8 @@ ar5212GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked)
mask2 |= HAL_INT_DTIMSYNC;
if (isr2 & AR_ISR_S2_CABEND)
mask2 |= HAL_INT_CABEND;
if (isr2 & AR_ISR_S2_TBTT)
mask2 |= HAL_INT_TBTT;
}
isr = OS_REG_READ(ah, AR_ISR_RAC);
if (isr == 0xffffffff) {
@ -172,6 +174,8 @@ ar5212SetInterrupts(struct ath_hal *ah, HAL_INT ints)
mask2 |= AR_IMR_S2_DTIMSYNC;
if (ints & HAL_INT_CABEND)
mask2 |= AR_IMR_S2_CABEND;
if (ints & HAL_INT_TBTT)
mask2 |= AR_IMR_S2_TBTT;
}
if (ints & HAL_INT_FATAL) {
/*

10
sys/dev/ath/ath_hal/ar5212/ar5212reg.h
View file

@ -463,7 +463,8 @@
#define AR_ISR_S2_BCNTO 0x08000000 /* BCNTO */
#define AR_ISR_S2_CABTO 0x10000000 /* CABTO */
#define AR_ISR_S2_DTIM 0x20000000 /* DTIM */
#define AR_ISR_S2_RESV0 0xE0F8FC00 /* Reserved */
#define AR_ISR_S2_TSFOOR 0x40000000 /* TSF OOR */
#define AR_ISR_S2_TBTT 0x80000000 /* TBTT timer */
#define AR_ISR_S3_QCU_QCBROVF 0x000003FF /* Mask for QCBROVF (QCU 0-9) */
#define AR_ISR_S3_QCU_QCBRURN 0x03FF0000 /* Mask for QCBRURN (QCU 0-9) */
@ -531,13 +532,14 @@
#define AR_IMR_S2_BCNTO 0x08000000 /* BCNTO */
#define AR_IMR_S2_CABTO 0x10000000 /* CABTO */
#define AR_IMR_S2_DTIM 0x20000000 /* DTIM */
#define AR_IMR_S2_TSFOOR 0x80000000 /* TSF OOR */
#define AR_IMR_S2_RESV0 0xE0F8FC00 /* Reserved */
#define AR_IMR_S2_TSFOOR 0x40000000 /* TSF OOR */
#define AR_IMR_S2_TBTT 0x80000000 /* TBTT timer */
/* AR_IMR_SR2 bits that correspond to AR_IMR_BCNMISC */
#define AR_IMR_SR2_BCNMISC \
(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC | \
AR_IMR_S2_CABEND | AR_IMR_S2_CABTO | AR_IMR_S2_TSFOOR)
AR_IMR_S2_CABEND | AR_IMR_S2_CABTO | AR_IMR_S2_TSFOOR | \
AR_IMR_S2_TBTT)
#define AR_IMR_S3_QCU_QCBROVF 0x000003FF /* Mask for QCBROVF (QCU 0-9) */
#define AR_IMR_S3_QCU_QCBRURN 0x03FF0000 /* Mask for QCBRURN (QCU 0-9) */