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Fix confusing naming of Marvell ARM CPU specific routines.
- The contents of 'feroceon_cpufuncs' dispatch table was really dedicated for the new Sheeva CPU (in 88F6xxx and MV-78xxx SOCs), and NOT Feroceon. - Feroceon CPU (in 88F5xxx SOCs) appears as a regular ARM926EJ-S core and does not require dedicated routines. This will be accompanied by a file rename commit.
This commit is contained in:
parent
e7be09420c
commit
1ee5b3b422
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=186933
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@ -358,7 +358,7 @@ struct cpu_functions armv5_ec_cpufuncs = {
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};
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struct cpu_functions feroceon_cpufuncs = {
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struct cpu_functions sheeva_cpufuncs = {
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/* CPU functions */
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cpufunc_id, /* id */
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@ -368,7 +368,7 @@ struct cpu_functions feroceon_cpufuncs = {
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cpufunc_control, /* control */
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cpufunc_domains, /* Domain */
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feroceon_setttb, /* Setttb */
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sheeva_setttb, /* Setttb */
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cpufunc_faultstatus, /* Faultstatus */
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cpufunc_faultaddress, /* Faultaddress */
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@ -387,17 +387,17 @@ struct cpu_functions feroceon_cpufuncs = {
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armv5_ec_icache_sync_range, /* icache_sync_range */
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armv5_ec_dcache_wbinv_all, /* dcache_wbinv_all */
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feroceon_dcache_wbinv_range, /* dcache_wbinv_range */
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feroceon_dcache_inv_range, /* dcache_inv_range */
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feroceon_dcache_wb_range, /* dcache_wb_range */
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sheeva_dcache_wbinv_range, /* dcache_wbinv_range */
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sheeva_dcache_inv_range, /* dcache_inv_range */
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sheeva_dcache_wb_range, /* dcache_wb_range */
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armv5_ec_idcache_wbinv_all, /* idcache_wbinv_all */
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feroceon_idcache_wbinv_range, /* idcache_wbinv_all */
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sheeva_idcache_wbinv_range, /* idcache_wbinv_all */
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feroceon_l2cache_wbinv_all, /* l2cache_wbinv_all */
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feroceon_l2cache_wbinv_range, /* l2cache_wbinv_range */
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feroceon_l2cache_inv_range, /* l2cache_inv_range */
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feroceon_l2cache_wb_range, /* l2cache_wb_range */
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sheeva_l2cache_wbinv_all, /* l2cache_wbinv_all */
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sheeva_l2cache_wbinv_range, /* l2cache_wbinv_range */
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sheeva_l2cache_inv_range, /* l2cache_inv_range */
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sheeva_l2cache_wb_range, /* l2cache_wb_range */
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/* Other functions */
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@ -1000,7 +1000,7 @@ set_cpufuncs()
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cputype == CPU_ID_MV88FR571_VD ||
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cputype == CPU_ID_MV88FR571_41) {
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cpufuncs = feroceon_cpufuncs;
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cpufuncs = sheeva_cpufuncs;
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/*
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* Workaround for Marvell MV78100 CPU: Cache prefetch
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* mechanism may affect the cache coherency validity,
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@ -1011,12 +1011,12 @@ set_cpufuncs()
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*/
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if (cputype == CPU_ID_MV88FR571_VD ||
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cputype == CPU_ID_MV88FR571_41) {
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feroceon_control_ext(0xffffffff,
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sheeva_control_ext(0xffffffff,
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FC_DCACHE_STREAM_EN | FC_WR_ALLOC_EN |
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FC_BRANCH_TARG_BUF_DIS | FC_L2CACHE_EN |
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FC_L2_PREF_DIS);
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} else {
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feroceon_control_ext(0xffffffff,
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sheeva_control_ext(0xffffffff,
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FC_DCACHE_STREAM_EN | FC_WR_ALLOC_EN |
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FC_BRANCH_TARG_BUF_DIS | FC_L2CACHE_EN);
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}
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@ -34,12 +34,12 @@ __FBSDID("$FreeBSD$");
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#include <machine/param.h>
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.Lferoceon_cache_line_size:
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.Lsheeva_cache_line_size:
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.word _C_LABEL(arm_pdcache_line_size)
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.Lferoceon_asm_page_mask:
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.Lsheeva_asm_page_mask:
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.word _C_LABEL(PAGE_MASK)
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ENTRY(feroceon_setttb)
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ENTRY(sheeva_setttb)
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/* Disable irqs */
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mrs r2, cpsr
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orr r3, r2, #I32_bit | F32_bit
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@ -63,11 +63,11 @@ ENTRY(feroceon_setttb)
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mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
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RET
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ENTRY(feroceon_dcache_wbinv_range)
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ENTRY(sheeva_dcache_wbinv_range)
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str lr, [sp, #-4]!
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mrs lr, cpsr
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/* Start with cache line aligned address */
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ldr ip, .Lferoceon_cache_line_size
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ldr ip, .Lsheeva_cache_line_size
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ldr ip, [ip]
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sub ip, ip, #1
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and r2, r0, ip
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@ -76,7 +76,7 @@ ENTRY(feroceon_dcache_wbinv_range)
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bics r1, r1, ip
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bics r0, r0, ip
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ldr ip, .Lferoceon_asm_page_mask
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ldr ip, .Lsheeva_asm_page_mask
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and r2, r0, ip
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rsb r2, r2, #PAGE_SIZE
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cmp r1, r2
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@ -105,11 +105,11 @@ ENTRY(feroceon_dcache_wbinv_range)
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ldr lr, [sp], #4
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RET
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ENTRY(feroceon_idcache_wbinv_range)
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ENTRY(sheeva_idcache_wbinv_range)
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str lr, [sp, #-4]!
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mrs lr, cpsr
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/* Start with cache line aligned address */
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ldr ip, .Lferoceon_cache_line_size
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ldr ip, .Lsheeva_cache_line_size
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ldr ip, [ip]
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sub ip, ip, #1
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and r2, r0, ip
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@ -118,7 +118,7 @@ ENTRY(feroceon_idcache_wbinv_range)
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bics r1, r1, ip
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bics r0, r0, ip
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ldr ip, .Lferoceon_asm_page_mask
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ldr ip, .Lsheeva_asm_page_mask
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and r2, r0, ip
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rsb r2, r2, #PAGE_SIZE
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cmp r1, r2
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@ -136,7 +136,7 @@ ENTRY(feroceon_idcache_wbinv_range)
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msr cpsr_c, lr
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/* Invalidate and clean icache line by line */
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ldr r3, .Lferoceon_cache_line_size
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ldr r3, .Lsheeva_cache_line_size
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ldr r3, [r3]
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2:
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mcr p15, 0, r0, c7, c5, 1
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@ -156,11 +156,11 @@ ENTRY(feroceon_idcache_wbinv_range)
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ldr lr, [sp], #4
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RET
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ENTRY(feroceon_dcache_inv_range)
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ENTRY(sheeva_dcache_inv_range)
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str lr, [sp, #-4]!
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mrs lr, cpsr
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/* Start with cache line aligned address */
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ldr ip, .Lferoceon_cache_line_size
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ldr ip, .Lsheeva_cache_line_size
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ldr ip, [ip]
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sub ip, ip, #1
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and r2, r0, ip
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@ -169,7 +169,7 @@ ENTRY(feroceon_dcache_inv_range)
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bics r1, r1, ip
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bics r0, r0, ip
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ldr ip, .Lferoceon_asm_page_mask
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ldr ip, .Lsheeva_asm_page_mask
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and r2, r0, ip
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rsb r2, r2, #PAGE_SIZE
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cmp r1, r2
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@ -198,11 +198,11 @@ ENTRY(feroceon_dcache_inv_range)
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ldr lr, [sp], #4
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RET
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ENTRY(feroceon_dcache_wb_range)
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ENTRY(sheeva_dcache_wb_range)
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str lr, [sp, #-4]!
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mrs lr, cpsr
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/* Start with cache line aligned address */
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ldr ip, .Lferoceon_cache_line_size
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ldr ip, .Lsheeva_cache_line_size
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ldr ip, [ip]
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sub ip, ip, #1
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and r2, r0, ip
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@ -211,7 +211,7 @@ ENTRY(feroceon_dcache_wb_range)
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bics r1, r1, ip
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bics r0, r0, ip
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ldr ip, .Lferoceon_asm_page_mask
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ldr ip, .Lsheeva_asm_page_mask
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and r2, r0, ip
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rsb r2, r2, #PAGE_SIZE
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cmp r1, r2
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@ -240,11 +240,11 @@ ENTRY(feroceon_dcache_wb_range)
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ldr lr, [sp], #4
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RET
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ENTRY(feroceon_l2cache_wbinv_range)
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ENTRY(sheeva_l2cache_wbinv_range)
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str lr, [sp, #-4]!
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mrs lr, cpsr
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/* Start with cache line aligned address */
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ldr ip, .Lferoceon_cache_line_size
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ldr ip, .Lsheeva_cache_line_size
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ldr ip, [ip]
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sub ip, ip, #1
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and r2, r0, ip
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@ -253,7 +253,7 @@ ENTRY(feroceon_l2cache_wbinv_range)
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bics r1, r1, ip
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bics r0, r0, ip
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ldr ip, .Lferoceon_asm_page_mask
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ldr ip, .Lsheeva_asm_page_mask
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and r2, r0, ip
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rsb r2, r2, #PAGE_SIZE
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cmp r1, r2
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@ -284,11 +284,11 @@ ENTRY(feroceon_l2cache_wbinv_range)
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ldr lr, [sp], #4
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RET
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ENTRY(feroceon_l2cache_inv_range)
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ENTRY(sheeva_l2cache_inv_range)
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str lr, [sp, #-4]!
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mrs lr, cpsr
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/* Start with cache line aligned address */
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ldr ip, .Lferoceon_cache_line_size
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ldr ip, .Lsheeva_cache_line_size
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ldr ip, [ip]
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sub ip, ip, #1
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and r2, r0, ip
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@ -297,7 +297,7 @@ ENTRY(feroceon_l2cache_inv_range)
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bics r1, r1, ip
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bics r0, r0, ip
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ldr ip, .Lferoceon_asm_page_mask
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ldr ip, .Lsheeva_asm_page_mask
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and r2, r0, ip
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rsb r2, r2, #PAGE_SIZE
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cmp r1, r2
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@ -326,11 +326,11 @@ ENTRY(feroceon_l2cache_inv_range)
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ldr lr, [sp], #4
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RET
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ENTRY(feroceon_l2cache_wb_range)
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ENTRY(sheeva_l2cache_wb_range)
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str lr, [sp, #-4]!
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mrs lr, cpsr
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/* Start with cache line aligned address */
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ldr ip, .Lferoceon_cache_line_size
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ldr ip, .Lsheeva_cache_line_size
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ldr ip, [ip]
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sub ip, ip, #1
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and r2, r0, ip
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@ -339,7 +339,7 @@ ENTRY(feroceon_l2cache_wb_range)
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bics r1, r1, ip
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bics r0, r0, ip
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ldr ip, .Lferoceon_asm_page_mask
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ldr ip, .Lsheeva_asm_page_mask
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and r2, r0, ip
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rsb r2, r2, #PAGE_SIZE
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cmp r1, r2
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@ -368,14 +368,14 @@ ENTRY(feroceon_l2cache_wb_range)
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ldr lr, [sp], #4
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RET
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ENTRY(feroceon_l2cache_wbinv_all)
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ENTRY(sheeva_l2cache_wbinv_all)
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mov r0, #0
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mcr p15, 1, r0, c15, c9, 0 /* Clean L2 */
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mcr p15, 1, r0, c15, c11, 0 /* Invalidate L2 */
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mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
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RET
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ENTRY(feroceon_control_ext)
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ENTRY(sheeva_control_ext)
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mrc p15, 1, r3, c15, c1, 0 /* Read the control register */
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bic r2, r3, r0 /* Clear bits */
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eor r2, r2, r1 /* XOR bits */
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@ -74,7 +74,7 @@ void __startC(void);
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#ifdef CPU_XSCALE_81342
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#define cpu_l2cache_wbinv_all xscalec3_l2cache_purge
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#elif defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY)
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#define cpu_l2cache_wbinv_all feroceon_l2cache_wbinv_all
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#define cpu_l2cache_wbinv_all sheeva_l2cache_wbinv_all
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#else
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#define cpu_l2cache_wbinv_all()
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#endif
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@ -377,17 +377,17 @@ extern unsigned arm10_dcache_sets_inc;
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extern unsigned arm10_dcache_index_max;
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extern unsigned arm10_dcache_index_inc;
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u_int feroceon_control_ext (u_int, u_int);
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void feroceon_setttb (u_int);
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void feroceon_dcache_wbinv_range (vm_offset_t, vm_size_t);
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void feroceon_dcache_inv_range (vm_offset_t, vm_size_t);
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void feroceon_dcache_wb_range (vm_offset_t, vm_size_t);
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void feroceon_idcache_wbinv_range (vm_offset_t, vm_size_t);
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u_int sheeva_control_ext (u_int, u_int);
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void sheeva_setttb (u_int);
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void sheeva_dcache_wbinv_range (vm_offset_t, vm_size_t);
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void sheeva_dcache_inv_range (vm_offset_t, vm_size_t);
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void sheeva_dcache_wb_range (vm_offset_t, vm_size_t);
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void sheeva_idcache_wbinv_range (vm_offset_t, vm_size_t);
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void feroceon_l2cache_wbinv_range (vm_offset_t, vm_size_t);
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void feroceon_l2cache_inv_range (vm_offset_t, vm_size_t);
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void feroceon_l2cache_wb_range (vm_offset_t, vm_size_t);
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void feroceon_l2cache_wbinv_all (void);
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void sheeva_l2cache_wbinv_range (vm_offset_t, vm_size_t);
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void sheeva_l2cache_inv_range (vm_offset_t, vm_size_t);
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void sheeva_l2cache_wb_range (vm_offset_t, vm_size_t);
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void sheeva_l2cache_wbinv_all (void);
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#endif
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#ifdef CPU_ARM11
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