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https://github.com/freebsd/freebsd-src
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- Switch on the full 32-bit device ID to avoid collisions between the
vendor-specific device ids across vendors. - Include the revision in the dc_devs[] array instead of special casing the revid handling in dc_devtype(). - Use PCI bus accessors to read registers instead of pci_read_config() where possible. - Use an 8-bit write to update the latency timer. - Use PCIR_xxx constants and remove unused DC_xxx related to standard PCI config registers. MFC after: 1 week
This commit is contained in:
John Baldwin
parent
344823993b
commit
1e2e70b1d6
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=159202
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@ -150,77 +150,75 @@ MODULE_DEPEND(dc, miibus, 1, 1, 1);
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* Various supported device vendors/types and their names.
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*/
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static struct dc_type dc_devs[] = {
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{ DC_VENDORID_DEC, DC_DEVICEID_21143,
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{ DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143), 0,
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"Intel 21143 10/100BaseTX" },
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{ DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009,
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{ DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009), 0,
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"Davicom DM9009 10/100BaseTX" },
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{ DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100,
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{ DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100), 0,
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"Davicom DM9100 10/100BaseTX" },
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{ DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102,
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"Davicom DM9102 10/100BaseTX" },
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{ DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102,
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{ DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), DC_REVISION_DM9102A,
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"Davicom DM9102A 10/100BaseTX" },
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{ DC_VENDORID_ADMTEK, DC_DEVICEID_AL981,
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{ DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), 0,
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"Davicom DM9102 10/100BaseTX" },
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{ DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981), 0,
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"ADMtek AL981 10/100BaseTX" },
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{ DC_VENDORID_ADMTEK, DC_DEVICEID_AN985,
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{ DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985), 0,
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"ADMtek AN985 10/100BaseTX" },
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{ DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511,
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{ DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511), 0,
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"ADMtek ADM9511 10/100BaseTX" },
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{ DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513,
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{ DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513), 0,
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"ADMtek ADM9513 10/100BaseTX" },
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{ DC_VENDORID_ADMTEK, DC_DEVICEID_FA511,
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{ DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_FA511), 0,
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"Netgear FA511 10/100BaseTX" },
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{ DC_VENDORID_ASIX, DC_DEVICEID_AX88140A,
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"ASIX AX88140A 10/100BaseTX" },
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{ DC_VENDORID_ASIX, DC_DEVICEID_AX88140A,
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{ DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), DC_REVISION_88141,
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"ASIX AX88141 10/100BaseTX" },
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{ DC_VENDORID_MX, DC_DEVICEID_98713,
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"Macronix 98713 10/100BaseTX" },
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{ DC_VENDORID_MX, DC_DEVICEID_98713,
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{ DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), 0,
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"ASIX AX88140A 10/100BaseTX" },
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{ DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), DC_REVISION_98713A,
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"Macronix 98713A 10/100BaseTX" },
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{ DC_VENDORID_CP, DC_DEVICEID_98713_CP,
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{ DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), 0,
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"Macronix 98713 10/100BaseTX" },
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{ DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), DC_REVISION_98713A,
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"Compex RL100-TX 10/100BaseTX" },
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{ DC_VENDORID_CP, DC_DEVICEID_98713_CP,
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{ DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), 0,
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"Compex RL100-TX 10/100BaseTX" },
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{ DC_VENDORID_MX, DC_DEVICEID_987x5,
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"Macronix 98715/98715A 10/100BaseTX" },
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{ DC_VENDORID_MX, DC_DEVICEID_987x5,
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"Macronix 98715AEC-C 10/100BaseTX" },
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{ DC_VENDORID_MX, DC_DEVICEID_987x5,
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{ DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98725,
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"Macronix 98725 10/100BaseTX" },
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{ DC_VENDORID_MX, DC_DEVICEID_98727,
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{ DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98715AEC_C,
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"Macronix 98715AEC-C 10/100BaseTX" },
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{ DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), 0,
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"Macronix 98715/98715A 10/100BaseTX" },
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{ DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727), 0,
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"Macronix 98727/98732 10/100BaseTX" },
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{ DC_VENDORID_LO, DC_DEVICEID_82C115,
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{ DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115), 0,
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"LC82C115 PNIC II 10/100BaseTX" },
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{ DC_VENDORID_LO, DC_DEVICEID_82C168,
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"82c168 PNIC 10/100BaseTX" },
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{ DC_VENDORID_LO, DC_DEVICEID_82C168,
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{ DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), DC_REVISION_82C169,
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"82c169 PNIC 10/100BaseTX" },
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{ DC_VENDORID_ACCTON, DC_DEVICEID_EN1217,
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{ DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), 0,
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"82c168 PNIC 10/100BaseTX" },
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{ DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217), 0,
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"Accton EN1217 10/100BaseTX" },
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{ DC_VENDORID_ACCTON, DC_DEVICEID_EN2242,
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{ DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242), 0,
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"Accton EN2242 MiniPCI 10/100BaseTX" },
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{ DC_VENDORID_XIRCOM, DC_DEVICEID_X3201,
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{ DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201), 0,
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"Xircom X3201 10/100BaseTX" },
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{ DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD,
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{ DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD), 0,
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"Neteasy DRP-32TXD Cardbus 10/100" },
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{ DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500,
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{ DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500), 0,
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"Abocom FE2500 10/100BaseTX" },
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{ DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX,
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{ DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX), 0,
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"Abocom FE2500MX 10/100BaseTX" },
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{ DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112,
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{ DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112), 0,
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"Conexant LANfinity MiniPCI 10/100BaseTX" },
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{ DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX,
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{ DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX), 0,
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"Hawking CB102 CardBus 10/100" },
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{ DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T,
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{ DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T), 0,
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"PlaneX FNW-3602-T CardBus 10/100" },
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{ DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB,
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{ DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB), 0,
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"3Com OfficeConnect 10/100B" },
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{ DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120,
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{ DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120), 0,
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"Microsoft MN-120 CardBus 10/100" },
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{ DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130,
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"Microsoft MN-130 10/100" },
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{ DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130_FAKE,
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{ DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130), 0,
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"Microsoft MN-130 10/100" },
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{ 0, 0, NULL }
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};
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@ -1003,7 +1001,7 @@ dc_miibus_mediainit(device_t dev)
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struct ifmedia *ifm;
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int rev;
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rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF;
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rev = pci_get_revid(dev);
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sc = device_get_softc(dev);
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mii = device_get_softc(sc->dc_miibus);
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@ -1560,50 +1558,16 @@ static struct dc_type *
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dc_devtype(device_t dev)
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{
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struct dc_type *t;
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u_int32_t rev;
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u_int32_t devid;
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u_int8_t rev;
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t = dc_devs;
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devid = pci_get_devid(dev);
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rev = pci_get_revid(dev);
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while (t->dc_name != NULL) {
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if ((pci_get_vendor(dev) == t->dc_vid) &&
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(pci_get_device(dev) == t->dc_did)) {
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/* Check the PCI revision */
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rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF;
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if (t->dc_did == DC_DEVICEID_98713 &&
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rev >= DC_REVISION_98713A)
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t++;
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if (t->dc_did == DC_DEVICEID_98713_CP &&
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rev >= DC_REVISION_98713A)
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t++;
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if (t->dc_did == DC_DEVICEID_987x5 &&
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rev >= DC_REVISION_98715AEC_C)
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t++;
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if (t->dc_did == DC_DEVICEID_987x5 &&
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rev >= DC_REVISION_98725)
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t++;
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if (t->dc_did == DC_DEVICEID_AX88140A &&
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rev >= DC_REVISION_88141)
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t++;
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if (t->dc_did == DC_DEVICEID_82C168 &&
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rev >= DC_REVISION_82C169)
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t++;
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if (t->dc_did == DC_DEVICEID_DM9102 &&
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rev >= DC_REVISION_DM9102A)
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t++;
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/*
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* The Microsoft MN-130 has a device ID of 0x0002,
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* which happens to be the same as the PNIC 82c168.
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* To keep dc_attach() from getting confused, we
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* pretend its ID is something different.
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* XXX: ideally, dc_attach() should be checking
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* vendorid+deviceid together to avoid such
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* collisions.
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*/
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if (t->dc_vid == DC_VENDORID_MICROSOFT &&
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t->dc_did == DC_DEVICEID_MSMN130)
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t++;
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if (devid == t->dc_devid && rev >= t->dc_minrev)
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return (t);
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}
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t++;
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}
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@ -1881,53 +1845,55 @@ dc_attach(device_t dev)
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/* Need this info to decide on a chip type. */
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sc->dc_info = dc_devtype(dev);
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revision = pci_read_config(dev, DC_PCI_CFRV, 4) & 0x000000FF;
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revision = pci_get_revid(dev);
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/* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */
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if (sc->dc_info->dc_did != DC_DEVICEID_82C168 &&
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sc->dc_info->dc_did != DC_DEVICEID_X3201)
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if (sc->dc_info->dc_devid !=
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DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168) &&
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sc->dc_info->dc_devid !=
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DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201))
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dc_eeprom_width(sc);
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switch (sc->dc_info->dc_did) {
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case DC_DEVICEID_21143:
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switch (sc->dc_info->dc_devid) {
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case DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143):
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sc->dc_type = DC_TYPE_21143;
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sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR;
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sc->dc_flags |= DC_REDUCED_MII_POLL;
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/* Save EEPROM contents so we can parse them later. */
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dc_read_srom(sc, sc->dc_romwidth);
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break;
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case DC_DEVICEID_DM9009:
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case DC_DEVICEID_DM9100:
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case DC_DEVICEID_DM9102:
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case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009):
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case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100):
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case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102):
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sc->dc_type = DC_TYPE_DM9102;
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sc->dc_flags |= DC_TX_COALESCE | DC_TX_INTR_ALWAYS;
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sc->dc_flags |= DC_REDUCED_MII_POLL | DC_TX_STORENFWD;
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sc->dc_flags |= DC_TX_ALIGN;
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sc->dc_pmode = DC_PMODE_MII;
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/* Increase the latency timer value. */
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command = pci_read_config(dev, DC_PCI_CFLT, 4);
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command &= 0xFFFF00FF;
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command |= 0x00008000;
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pci_write_config(dev, DC_PCI_CFLT, command, 4);
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pci_write_config(dev, PCIR_LATTIMER, 0x80, 1);
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break;
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case DC_DEVICEID_AL981:
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case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981):
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sc->dc_type = DC_TYPE_AL981;
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sc->dc_flags |= DC_TX_USE_TX_INTR;
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sc->dc_flags |= DC_TX_ADMTEK_WAR;
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sc->dc_pmode = DC_PMODE_MII;
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dc_read_srom(sc, sc->dc_romwidth);
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break;
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case DC_DEVICEID_AN985:
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case DC_DEVICEID_ADM9511:
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case DC_DEVICEID_ADM9513:
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case DC_DEVICEID_DRP32TXD:
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case DC_DEVICEID_FA511:
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case DC_DEVICEID_FE2500:
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case DC_DEVICEID_EN2242:
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case DC_DEVICEID_HAWKING_PN672TX:
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case DC_DEVICEID_3CSOHOB:
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case DC_DEVICEID_MSMN120:
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case DC_DEVICEID_MSMN130_FAKE: /* XXX avoid collision with PNIC*/
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case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985):
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case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511):
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case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513):
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case DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD):
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case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_FA511):
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case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500):
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case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX):
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case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242):
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case DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX):
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case DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T):
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case DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB):
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case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120):
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case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130):
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sc->dc_type = DC_TYPE_AN985;
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sc->dc_flags |= DC_64BIT_HASH;
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sc->dc_flags |= DC_TX_USE_TX_INTR;
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@ -1935,8 +1901,8 @@ dc_attach(device_t dev)
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sc->dc_pmode = DC_PMODE_MII;
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/* Don't read SROM for - auto-loaded on reset */
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break;
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case DC_DEVICEID_98713:
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case DC_DEVICEID_98713_CP:
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case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713):
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case DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP):
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if (revision < DC_REVISION_98713A) {
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sc->dc_type = DC_TYPE_98713;
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}
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@ -1947,8 +1913,8 @@ dc_attach(device_t dev)
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sc->dc_flags |= DC_REDUCED_MII_POLL;
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sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR;
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break;
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case DC_DEVICEID_987x5:
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case DC_DEVICEID_EN1217:
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case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5):
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case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217):
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/*
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* Macronix MX98715AEC-C/D/E parts have only a
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* 128-bit hash table. We need to deal with these
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@ -1963,17 +1929,17 @@ dc_attach(device_t dev)
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sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR;
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sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY;
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break;
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case DC_DEVICEID_98727:
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case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727):
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sc->dc_type = DC_TYPE_987x5;
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sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR;
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sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY;
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break;
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case DC_DEVICEID_82C115:
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case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115):
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sc->dc_type = DC_TYPE_PNICII;
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sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR | DC_128BIT_HASH;
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sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY;
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break;
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case DC_DEVICEID_82C168:
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case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168):
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sc->dc_type = DC_TYPE_PNIC;
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sc->dc_flags |= DC_TX_STORENFWD | DC_TX_INTR_ALWAYS;
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sc->dc_flags |= DC_PNIC_RX_BUG_WAR;
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@ -1981,13 +1947,13 @@ dc_attach(device_t dev)
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if (revision < DC_REVISION_82C169)
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sc->dc_pmode = DC_PMODE_SYM;
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break;
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||||
case DC_DEVICEID_AX88140A:
|
||||
case DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A):
|
||||
sc->dc_type = DC_TYPE_ASIX;
|
||||
sc->dc_flags |= DC_TX_USE_TX_INTR | DC_TX_INTR_FIRSTFRAG;
|
||||
sc->dc_flags |= DC_REDUCED_MII_POLL;
|
||||
sc->dc_pmode = DC_PMODE_MII;
|
||||
break;
|
||||
case DC_DEVICEID_X3201:
|
||||
case DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201):
|
||||
sc->dc_type = DC_TYPE_XIRCOM;
|
||||
sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE |
|
||||
DC_TX_ALIGN;
|
||||
|
|
@ -1998,7 +1964,7 @@ dc_attach(device_t dev)
|
|||
*/
|
||||
sc->dc_pmode = DC_PMODE_MII;
|
||||
break;
|
||||
case DC_DEVICEID_RS7112:
|
||||
case DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112):
|
||||
sc->dc_type = DC_TYPE_CONEXANT;
|
||||
sc->dc_flags |= DC_TX_INTR_ALWAYS;
|
||||
sc->dc_flags |= DC_REDUCED_MII_POLL;
|
||||
|
|
@ -2006,7 +1972,8 @@ dc_attach(device_t dev)
|
|||
dc_read_srom(sc, sc->dc_romwidth);
|
||||
break;
|
||||
default:
|
||||
device_printf(dev, "unknown device: %x\n", sc->dc_info->dc_did);
|
||||
device_printf(dev, "unknown device: %x\n",
|
||||
sc->dc_info->dc_devid);
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
@ -2014,8 +1981,7 @@ dc_attach(device_t dev)
|
|||
if (DC_IS_DAVICOM(sc))
|
||||
sc->dc_cachesize = 0;
|
||||
else
|
||||
sc->dc_cachesize = pci_read_config(dev,
|
||||
DC_PCI_CFLT, 4) & 0xFF;
|
||||
sc->dc_cachesize = pci_get_cachelnsz(dev);
|
||||
|
||||
/* Reset the adapter. */
|
||||
dc_reset(sc);
|
||||
|
|
@ -2249,7 +2215,8 @@ dc_attach(device_t dev)
|
|||
* LEDs, and twiddling these bits has adverse effects
|
||||
* on them. (I.e. you suddenly can't get a link.)
|
||||
*/
|
||||
if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033)
|
||||
if (!(pci_get_subvendor(dev) == 0x1033 &&
|
||||
pci_get_subdevice(dev) == 0x8028))
|
||||
sc->dc_flags |= DC_TULIP_LEDS;
|
||||
error = 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -512,8 +512,8 @@ struct dc_mediainfo {
|
|||
|
||||
|
||||
struct dc_type {
|
||||
u_int16_t dc_vid;
|
||||
u_int16_t dc_did;
|
||||
u_int32_t dc_devid;
|
||||
u_int8_t dc_minrev;
|
||||
char *dc_name;
|
||||
};
|
||||
|
||||
|
|
@ -1004,58 +1004,22 @@ struct dc_softc {
|
|||
|
||||
#define DC_DEVICEID_MSMN120 0x0001
|
||||
#define DC_DEVICEID_MSMN130 0x0002
|
||||
#define DC_DEVICEID_MSMN130_FAKE 0xFFF2
|
||||
|
||||
#define DC_DEVID(vendor, device) ((device) << 16 | (vendor))
|
||||
|
||||
/*
|
||||
* PCI low memory base and low I/O base register, and
|
||||
* other PCI registers.
|
||||
*/
|
||||
|
||||
#define DC_PCI_CFID 0x00 /* Id */
|
||||
#define DC_PCI_CFCS 0x04 /* Command and status */
|
||||
#define DC_PCI_CFRV 0x08 /* Revision */
|
||||
#define DC_PCI_CFLT 0x0C /* Latency timer */
|
||||
#define DC_PCI_CFBIO 0x10 /* Base I/O address */
|
||||
#define DC_PCI_CFBMA 0x14 /* Base memory address */
|
||||
#define DC_PCI_CCIS 0x28 /* Card info struct */
|
||||
#define DC_PCI_CSID 0x2C /* Subsystem ID */
|
||||
#define DC_PCI_CBER 0x30 /* Expansion ROM base address */
|
||||
#define DC_PCI_CCAP 0x34 /* Caps pointer - PD/TD chip only */
|
||||
#define DC_PCI_CFIT 0x3C /* Interrupt */
|
||||
#define DC_PCI_CFBIO PCIR_BAR(0) /* Base I/O address */
|
||||
#define DC_PCI_CFBMA PCIR_BAR(1) /* Base memory address */
|
||||
#define DC_PCI_CFDD 0x40 /* Device and driver area */
|
||||
#define DC_PCI_CWUA0 0x44 /* Wake-Up LAN addr 0 */
|
||||
#define DC_PCI_CWUA1 0x48 /* Wake-Up LAN addr 1 */
|
||||
#define DC_PCI_SOP0 0x4C /* SecureON passwd 0 */
|
||||
#define DC_PCI_SOP1 0x50 /* SecureON passwd 1 */
|
||||
#define DC_PCI_CWUC 0x54 /* Configuration Wake-Up cmd */
|
||||
#define DC_PCI_CCID 0xDC /* Capability ID - PD/TD only */
|
||||
#define DC_PCI_CPMC 0xE0 /* Pwrmgmt ctl & sts - PD/TD only */
|
||||
|
||||
/* PCI ID register */
|
||||
#define DC_CFID_VENDOR 0x0000FFFF
|
||||
#define DC_CFID_DEVICE 0xFFFF0000
|
||||
|
||||
/* PCI command/status register */
|
||||
#define DC_CFCS_IOSPACE 0x00000001 /* I/O space enable */
|
||||
#define DC_CFCS_MEMSPACE 0x00000002 /* memory space enable */
|
||||
#define DC_CFCS_BUSMASTER 0x00000004 /* bus master enable */
|
||||
#define DC_CFCS_MWI_ENB 0x00000010 /* mem write and inval enable */
|
||||
#define DC_CFCS_PARITYERR_ENB 0x00000040 /* parity error enable */
|
||||
#define DC_CFCS_SYSERR_ENB 0x00000100 /* system error enable */
|
||||
#define DC_CFCS_NEWCAPS 0x00100000 /* new capabilities */
|
||||
#define DC_CFCS_FAST_B2B 0x00800000 /* fast back-to-back capable */
|
||||
#define DC_CFCS_DATAPARITY 0x01000000 /* Parity error report */
|
||||
#define DC_CFCS_DEVSELTIM 0x06000000 /* devsel timing */
|
||||
#define DC_CFCS_TGTABRT 0x10000000 /* received target abort */
|
||||
#define DC_CFCS_MASTERABRT 0x20000000 /* received master abort */
|
||||
#define DC_CFCS_SYSERR 0x40000000 /* asserted system error */
|
||||
#define DC_CFCS_PARITYERR 0x80000000 /* asserted parity error */
|
||||
|
||||
/* PCI revision register */
|
||||
#define DC_CFRV_STEPPING 0x0000000F
|
||||
#define DC_CFRV_REVISION 0x000000F0
|
||||
#define DC_CFRV_SUBCLASS 0x00FF0000
|
||||
#define DC_CFRV_BASECLASS 0xFF000000
|
||||
|
||||
#define DC_21143_PB_REV 0x00000030
|
||||
#define DC_21143_TB_REV 0x00000030
|
||||
|
|
@ -1064,48 +1028,6 @@ struct dc_softc {
|
|||
#define DC_21143_PD_REV 0x00000041
|
||||
#define DC_21143_TD_REV 0x00000041
|
||||
|
||||
/* PCI latency timer register */
|
||||
#define DC_CFLT_CACHELINESIZE 0x000000FF
|
||||
#define DC_CFLT_LATENCYTIMER 0x0000FF00
|
||||
|
||||
/* PCI subsystem ID register */
|
||||
#define DC_CSID_VENDOR 0x0000FFFF
|
||||
#define DC_CSID_DEVICE 0xFFFF0000
|
||||
|
||||
/* PCI cababilities pointer */
|
||||
#define DC_CCAP_OFFSET 0x000000FF
|
||||
|
||||
/* PCI interrupt config register */
|
||||
#define DC_CFIT_INTLINE 0x000000FF
|
||||
#define DC_CFIT_INTPIN 0x0000FF00
|
||||
#define DC_CFIT_MIN_GNT 0x00FF0000
|
||||
#define DC_CFIT_MAX_LAT 0xFF000000
|
||||
|
||||
/* PCI capability register */
|
||||
#define DC_CCID_CAPID 0x000000FF
|
||||
#define DC_CCID_NEXTPTR 0x0000FF00
|
||||
#define DC_CCID_PM_VERS 0x00070000
|
||||
#define DC_CCID_PME_CLK 0x00080000
|
||||
#define DC_CCID_DVSPEC_INT 0x00200000
|
||||
#define DC_CCID_STATE_D1 0x02000000
|
||||
#define DC_CCID_STATE_D2 0x04000000
|
||||
#define DC_CCID_PME_D0 0x08000000
|
||||
#define DC_CCID_PME_D1 0x10000000
|
||||
#define DC_CCID_PME_D2 0x20000000
|
||||
#define DC_CCID_PME_D3HOT 0x40000000
|
||||
#define DC_CCID_PME_D3COLD 0x80000000
|
||||
|
||||
/* PCI power management control/status register */
|
||||
#define DC_CPMC_STATE 0x00000003
|
||||
#define DC_CPMC_PME_ENB 0x00000100
|
||||
#define DC_CPMC_PME_STS 0x00008000
|
||||
|
||||
#define DC_PSTATE_D0 0x0
|
||||
#define DC_PSTATE_D1 0x1
|
||||
#define DC_PSTATE_D2 0x2
|
||||
#define DC_PSTATE_D3 0x3
|
||||
|
||||
/* Device specific region */
|
||||
/* Configuration and driver area */
|
||||
#define DC_CFDD_DRVUSE 0x0000FFFF
|
||||
#define DC_CFDD_SNOOZE_MODE 0x40000000
|
||||
|
|
|
|||
Loading…
Reference in a new issue