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Add symmetric crypto support for the 7955 and 7956.
Note performance is currently suboptimal. Submitted by: Rajesh Vaidyanath <RVaidyanath@hifn.com>
This commit is contained in:
Sam Leffler
parent
f3e533d270
commit
17b667019e
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=120915
3 changed files with 159 additions and 41 deletions
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@ -6,6 +6,7 @@
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* Copyright (c) 1999 Theo de Raadt
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* Copyright (c) 2000-2001 Network Security Technologies, Inc.
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* http://www.netsec.net
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* Copyright (c) 2003 Hifn Inc.
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*
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* This driver is based on a previous driver by Invertex, for which they
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* requested: Please send any comments, feedback, bug-fixes, or feature
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@ -43,7 +44,7 @@
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__FBSDID("$FreeBSD$");
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/*
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* Driver for the Hifn 7751 encryption processor.
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* Driver for various Hifn encryption processors.
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*/
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#include "opt_hifn.h"
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@ -195,6 +196,8 @@ hifn_probe(device_t dev)
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if (pci_get_vendor(dev) == PCI_VENDOR_HIFN &&
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(pci_get_device(dev) == PCI_PRODUCT_HIFN_7751 ||
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pci_get_device(dev) == PCI_PRODUCT_HIFN_7951 ||
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pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 ||
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pci_get_device(dev) == PCI_PRODUCT_HIFN_7956 ||
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pci_get_device(dev) == PCI_PRODUCT_HIFN_7811))
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return (0);
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if (pci_get_vendor(dev) == PCI_VENDOR_NETSEC &&
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@ -221,6 +224,8 @@ hifn_partname(struct hifn_softc *sc)
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case PCI_PRODUCT_HIFN_7751: return "Hifn 7751";
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case PCI_PRODUCT_HIFN_7811: return "Hifn 7811";
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case PCI_PRODUCT_HIFN_7951: return "Hifn 7951";
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case PCI_PRODUCT_HIFN_7955: return "Hifn 7955";
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case PCI_PRODUCT_HIFN_7956: return "Hifn 7956";
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}
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return "Hifn unknown-part";
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case PCI_VENDOR_INVERTEX:
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@ -265,11 +270,13 @@ hifn_attach(device_t dev)
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/* XXX handle power management */
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/*
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* The 7951 has a random number generator and
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* The 7951 and 795x have a random number generator and
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* public key support; note this.
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*/
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if (pci_get_vendor(dev) == PCI_VENDOR_HIFN &&
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pci_get_device(dev) == PCI_PRODUCT_HIFN_7951)
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(pci_get_device(dev) == PCI_PRODUCT_HIFN_7951 ||
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pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 ||
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pci_get_device(dev) == PCI_PRODUCT_HIFN_7956))
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sc->sc_flags = HIFN_HAS_RNG | HIFN_HAS_PUBLIC;
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/*
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* The 7811 has a random number generator and
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@ -279,6 +286,14 @@ hifn_attach(device_t dev)
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pci_get_device(dev) == PCI_PRODUCT_HIFN_7811)
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sc->sc_flags |= HIFN_IS_7811 | HIFN_HAS_RNG;
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/*
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* The 795x parts support AES.
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*/
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if (pci_get_vendor(dev) == PCI_VENDOR_HIFN &&
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(pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 ||
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pci_get_device(dev) == PCI_PRODUCT_HIFN_7956))
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sc->sc_flags |= HIFN_IS_7956 | HIFN_HAS_AES;
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/*
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* Configure support for memory-mapped access to
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* registers and for DMA operations.
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@ -395,7 +410,10 @@ hifn_attach(device_t dev)
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hifn_init_dma(sc);
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hifn_init_pci_registers(sc);
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if (hifn_ramtype(sc))
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/* XXX can't dynamically determine ram type for 795x; force dram */
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if (sc->sc_flags & HIFN_IS_7956)
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sc->sc_drammodel = 1;
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else if (hifn_ramtype(sc))
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goto fail_mem;
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if (sc->sc_drammodel == 0)
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@ -467,6 +485,10 @@ hifn_attach(device_t dev)
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hifn_newsession, hifn_freesession, hifn_process, sc);
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crypto_register(sc->sc_cid, CRYPTO_ARC4, 0, 0,
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hifn_newsession, hifn_freesession, hifn_process, sc);
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if (sc->sc_flags & HIFN_HAS_AES)
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crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0,
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hifn_newsession, hifn_freesession,
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hifn_process, sc);
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/*FALLTHROUGH*/
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case HIFN_PUSTAT_ENA_1:
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crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0,
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@ -874,6 +896,16 @@ static struct pci2id pci2id[] = {
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PCI_PRODUCT_HIFN_7951,
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{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00 }
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}, {
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PCI_VENDOR_HIFN,
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PCI_PRODUCT_HIFN_7955,
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{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00 }
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}, {
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PCI_VENDOR_HIFN,
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PCI_PRODUCT_HIFN_7956,
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{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00 }
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}, {
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PCI_VENDOR_NETSEC,
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PCI_PRODUCT_NETSEC_7751,
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@ -1055,10 +1087,18 @@ hifn_init_pci_registers(struct hifn_softc *sc)
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sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT;
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WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier);
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WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING |
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HIFN_PUCNFG_DRFR_128 | HIFN_PUCNFG_TCALLPHASES |
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HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32 |
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(sc->sc_drammodel ? HIFN_PUCNFG_DRAM : HIFN_PUCNFG_SRAM));
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if (sc->sc_flags & HIFN_IS_7956) {
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WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING |
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HIFN_PUCNFG_TCALLPHASES |
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HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32);
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WRITE_REG_1(sc, HIFN_1_PLL, HIFN_PLL_7956);
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} else {
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WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING |
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HIFN_PUCNFG_DRFR_128 | HIFN_PUCNFG_TCALLPHASES |
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HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32 |
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(sc->sc_drammodel ? HIFN_PUCNFG_DRAM : HIFN_PUCNFG_SRAM));
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}
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WRITE_REG_0(sc, HIFN_0_PUISR, HIFN_PUISR_DSTOVER);
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WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
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@ -1087,8 +1127,14 @@ hifn_sessions(struct hifn_softc *sc)
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ctxsize = 128;
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else
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ctxsize = 512;
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sc->sc_maxses = 1 +
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((sc->sc_ramsize - 32768) / ctxsize);
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/*
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* 7955/7956 has internal context memory of 32K
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*/
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if (sc->sc_flags & HIFN_IS_7956)
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sc->sc_maxses = 32768 / ctxsize;
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else
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sc->sc_maxses = 1 +
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((sc->sc_ramsize - 32768) / ctxsize);
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} else
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sc->sc_maxses = sc->sc_ramsize / 16384;
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@ -1175,9 +1221,16 @@ hifn_dramsize(struct hifn_softc *sc)
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{
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u_int32_t cnfg;
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cnfg = READ_REG_0(sc, HIFN_0_PUCNFG) &
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HIFN_PUCNFG_DRAMMASK;
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sc->sc_ramsize = 1 << ((cnfg >> 13) + 18);
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if (sc->sc_flags & HIFN_IS_7956) {
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/*
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* 7955/7956 have a fixed internal ram of only 32K.
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*/
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sc->sc_ramsize = 32768;
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} else {
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cnfg = READ_REG_0(sc, HIFN_0_PUCNFG) &
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HIFN_PUCNFG_DRAMMASK;
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sc->sc_ramsize = 1 << ((cnfg >> 13) + 18);
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}
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return (0);
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}
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@ -1393,7 +1446,7 @@ hifn_write_command(struct hifn_command *cmd, u_int8_t *buf)
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hifn_base_command_t *base_cmd;
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hifn_mac_command_t *mac_cmd;
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hifn_crypt_command_t *cry_cmd;
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int using_mac, using_crypt, len;
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int using_mac, using_crypt, len, ivlen;
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u_int32_t dlen, slen;
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buf_pos = buf;
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@ -1453,7 +1506,7 @@ hifn_write_command(struct hifn_command *cmd, u_int8_t *buf)
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break;
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case HIFN_CRYPT_CMD_ALG_DES:
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bcopy(cmd->ck, buf_pos, HIFN_DES_KEY_LENGTH);
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buf_pos += cmd->cklen;
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buf_pos += HIFN_DES_KEY_LENGTH;
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break;
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case HIFN_CRYPT_CMD_ALG_RC4:
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len = 256;
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@ -1468,12 +1521,28 @@ hifn_write_command(struct hifn_command *cmd, u_int8_t *buf)
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bzero(buf_pos, 4);
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buf_pos += 4;
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break;
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case HIFN_CRYPT_CMD_ALG_AES:
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/*
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* AES keys are variable 128, 192 and
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* 256 bits (16, 24 and 32 bytes).
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*/
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bcopy(cmd->ck, buf_pos, cmd->cklen);
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buf_pos += cmd->cklen;
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break;
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}
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}
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if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_IV) {
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bcopy(cmd->iv, buf_pos, HIFN_IV_LENGTH);
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buf_pos += HIFN_IV_LENGTH;
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switch (cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) {
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case HIFN_CRYPT_CMD_ALG_AES:
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ivlen = HIFN_AES_IV_LENGTH;
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break;
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default:
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ivlen = HIFN_IV_LENGTH;
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break;
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}
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bcopy(cmd->iv, buf_pos, ivlen);
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buf_pos += ivlen;
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}
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if ((cmd->base_masks & (HIFN_BASE_CMD_MAC|HIFN_BASE_CMD_CRYPT)) == 0) {
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@ -2161,8 +2230,11 @@ hifn_newsession(void *arg, u_int32_t *sidp, struct cryptoini *cri)
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break;
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case CRYPTO_DES_CBC:
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case CRYPTO_3DES_CBC:
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case CRYPTO_AES_CBC:
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/* XXX this may read fewer, does it matter? */
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read_random(sc->sc_sessions[i].hs_iv, HIFN_IV_LENGTH);
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read_random(sc->sc_sessions[i].hs_iv,
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c->cri_alg == CRYPTO_AES_CBC ?
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HIFN_AES_IV_LENGTH : HIFN_IV_LENGTH);
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/*FALLTHROUGH*/
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case CRYPTO_ARC4:
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if (cry)
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@ -2211,7 +2283,7 @@ hifn_process(void *arg, struct cryptop *crp, int hint)
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{
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struct hifn_softc *sc = arg;
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struct hifn_command *cmd = NULL;
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int session, err;
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int session, err, ivlen;
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struct cryptodesc *crd1, *crd2, *maccrd, *enccrd;
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if (crp == NULL || crp->crp_callback == NULL) {
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@ -2259,6 +2331,7 @@ hifn_process(void *arg, struct cryptop *crp, int hint)
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enccrd = NULL;
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} else if (crd1->crd_alg == CRYPTO_DES_CBC ||
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crd1->crd_alg == CRYPTO_3DES_CBC ||
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crd1->crd_alg == CRYPTO_AES_CBC ||
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crd1->crd_alg == CRYPTO_ARC4) {
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if ((crd1->crd_flags & CRD_F_ENCRYPT) == 0)
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cmd->base_masks |= HIFN_BASE_CMD_DECODE;
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@ -2275,6 +2348,7 @@ hifn_process(void *arg, struct cryptop *crp, int hint)
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crd1->crd_alg == CRYPTO_SHA1) &&
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(crd2->crd_alg == CRYPTO_DES_CBC ||
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crd2->crd_alg == CRYPTO_3DES_CBC ||
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crd2->crd_alg == CRYPTO_AES_CBC ||
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crd2->crd_alg == CRYPTO_ARC4) &&
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((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) {
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cmd->base_masks = HIFN_BASE_CMD_DECODE;
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@ -2282,7 +2356,8 @@ hifn_process(void *arg, struct cryptop *crp, int hint)
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enccrd = crd2;
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} else if ((crd1->crd_alg == CRYPTO_DES_CBC ||
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crd1->crd_alg == CRYPTO_ARC4 ||
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crd1->crd_alg == CRYPTO_3DES_CBC) &&
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crd1->crd_alg == CRYPTO_3DES_CBC ||
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crd1->crd_alg == CRYPTO_AES_CBC) &&
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(crd2->crd_alg == CRYPTO_MD5_HMAC ||
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crd2->crd_alg == CRYPTO_SHA1_HMAC ||
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crd2->crd_alg == CRYPTO_MD5 ||
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@ -2320,48 +2395,72 @@ hifn_process(void *arg, struct cryptop *crp, int hint)
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HIFN_CRYPT_CMD_MODE_CBC |
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HIFN_CRYPT_CMD_NEW_IV;
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break;
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case CRYPTO_AES_CBC:
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cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_AES |
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HIFN_CRYPT_CMD_MODE_CBC |
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HIFN_CRYPT_CMD_NEW_IV;
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break;
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default:
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err = EINVAL;
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goto errout;
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}
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if (enccrd->crd_alg != CRYPTO_ARC4) {
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ivlen = ((enccrd->crd_alg == CRYPTO_AES_CBC) ?
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HIFN_AES_IV_LENGTH : HIFN_IV_LENGTH);
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if (enccrd->crd_flags & CRD_F_ENCRYPT) {
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if (enccrd->crd_flags & CRD_F_IV_EXPLICIT)
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bcopy(enccrd->crd_iv, cmd->iv,
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HIFN_IV_LENGTH);
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bcopy(enccrd->crd_iv, cmd->iv, ivlen);
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else
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bcopy(sc->sc_sessions[session].hs_iv,
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cmd->iv, HIFN_IV_LENGTH);
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cmd->iv, ivlen);
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if ((enccrd->crd_flags & CRD_F_IV_PRESENT)
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== 0) {
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if (crp->crp_flags & CRYPTO_F_IMBUF)
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m_copyback(cmd->src_m,
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enccrd->crd_inject,
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HIFN_IV_LENGTH, cmd->iv);
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ivlen, cmd->iv);
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else if (crp->crp_flags & CRYPTO_F_IOV)
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cuio_copyback(cmd->src_io,
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enccrd->crd_inject,
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HIFN_IV_LENGTH, cmd->iv);
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ivlen, cmd->iv);
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}
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} else {
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if (enccrd->crd_flags & CRD_F_IV_EXPLICIT)
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bcopy(enccrd->crd_iv, cmd->iv,
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HIFN_IV_LENGTH);
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bcopy(enccrd->crd_iv, cmd->iv, ivlen);
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else if (crp->crp_flags & CRYPTO_F_IMBUF)
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m_copydata(cmd->src_m,
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enccrd->crd_inject,
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HIFN_IV_LENGTH, cmd->iv);
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enccrd->crd_inject, ivlen, cmd->iv);
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else if (crp->crp_flags & CRYPTO_F_IOV)
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cuio_copydata(cmd->src_io,
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enccrd->crd_inject,
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HIFN_IV_LENGTH, cmd->iv);
|
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enccrd->crd_inject, ivlen, cmd->iv);
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}
|
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}
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|
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cmd->ck = enccrd->crd_key;
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cmd->cklen = enccrd->crd_klen >> 3;
|
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|
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/*
|
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* Need to specify the size for the AES key in the masks.
|
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*/
|
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if ((cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) ==
|
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HIFN_CRYPT_CMD_ALG_AES) {
|
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switch (cmd->cklen) {
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case 16:
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cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_128;
|
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break;
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case 24:
|
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cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_192;
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break;
|
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case 32:
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cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_256;
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break;
|
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default:
|
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err = EINVAL;
|
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goto errout;
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}
|
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}
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|
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if (sc->sc_sessions[session].hs_state == HS_STATE_USED)
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cmd->cry_masks |= HIFN_CRYPT_CMD_NEW_KEY;
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}
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|
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@ -2527,7 +2626,7 @@ hifn_callback(struct hifn_softc *sc, struct hifn_command *cmd, u_int8_t *macbuf)
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struct cryptop *crp = cmd->crp;
|
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struct cryptodesc *crd;
|
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struct mbuf *m;
|
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int totlen, i, u;
|
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int totlen, i, u, ivlen;
|
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|
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if (cmd->src_map == cmd->dst_map) {
|
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bus_dmamap_sync(sc->sc_dmat, cmd->src_map,
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|
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@ -2587,17 +2686,18 @@ hifn_callback(struct hifn_softc *sc, struct hifn_command *cmd, u_int8_t *macbuf)
|
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HIFN_BASE_CMD_CRYPT) {
|
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for (crd = crp->crp_desc; crd; crd = crd->crd_next) {
|
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if (crd->crd_alg != CRYPTO_DES_CBC &&
|
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crd->crd_alg != CRYPTO_3DES_CBC)
|
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crd->crd_alg != CRYPTO_3DES_CBC &&
|
||||
crd->crd_alg != CRYPTO_AES_CBC)
|
||||
continue;
|
||||
ivlen = ((crd->crd_alg == CRYPTO_AES_CBC) ?
|
||||
HIFN_AES_IV_LENGTH : HIFN_IV_LENGTH);
|
||||
if (crp->crp_flags & CRYPTO_F_IMBUF)
|
||||
m_copydata((struct mbuf *)crp->crp_buf,
|
||||
crd->crd_skip + crd->crd_len - HIFN_IV_LENGTH,
|
||||
HIFN_IV_LENGTH,
|
||||
crd->crd_skip + crd->crd_len - ivlen, ivlen,
|
||||
cmd->softc->sc_sessions[cmd->session_num].hs_iv);
|
||||
else if (crp->crp_flags & CRYPTO_F_IOV) {
|
||||
cuio_copydata((struct uio *)crp->crp_buf,
|
||||
crd->crd_skip + crd->crd_len - HIFN_IV_LENGTH,
|
||||
HIFN_IV_LENGTH,
|
||||
crd->crd_skip + crd->crd_len - ivlen, ivlen,
|
||||
cmd->softc->sc_sessions[cmd->session_num].hs_iv);
|
||||
}
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -63,6 +63,8 @@
|
|||
#define PCI_PRODUCT_HIFN_6500 0x0006 /* 6500 */
|
||||
#define PCI_PRODUCT_HIFN_7811 0x0007 /* 7811 */
|
||||
#define PCI_PRODUCT_HIFN_7951 0x0012 /* 7951 */
|
||||
#define PCI_PRODUCT_HIFN_7955 0x0020 /* 7954/7955 */
|
||||
#define PCI_PRODUCT_HIFN_7956 0x001d /* 7956 */
|
||||
|
||||
#define PCI_VENDOR_INVERTEX 0x14e1 /* Invertex */
|
||||
#define PCI_PRODUCT_INVERTEX_AEON 0x0005 /* AEON */
|
||||
|
|
@ -210,6 +212,7 @@ typedef struct hifn_desc {
|
|||
#define HIFN_1_DMA_CSR 0x40 /* DMA Status and Control */
|
||||
#define HIFN_1_DMA_IER 0x44 /* DMA Interrupt Enable */
|
||||
#define HIFN_1_DMA_CNFG 0x48 /* DMA Configuration */
|
||||
#define HIFN_1_PLL 0x4c /* 7955/7956: PLL config */
|
||||
#define HIFN_1_7811_RNGENA 0x60 /* 7811: rng enable */
|
||||
#define HIFN_1_7811_RNGCFG 0x64 /* 7811: rng config */
|
||||
#define HIFN_1_7811_RNGDAT 0x68 /* 7811: rng data */
|
||||
|
|
@ -369,6 +372,11 @@ typedef struct hifn_desc {
|
|||
#define HIFN_UNLOCK_SECRET1 0xf4
|
||||
#define HIFN_UNLOCK_SECRET2 0xfc
|
||||
|
||||
/*
|
||||
* PLL config register
|
||||
*/
|
||||
#define HIFN_PLL_7956 0x00001d18 /* 7956 PLL config value */
|
||||
|
||||
/*********************************************************************
|
||||
* Structs for board commands
|
||||
*
|
||||
|
|
@ -408,7 +416,8 @@ typedef struct hifn_crypt_command {
|
|||
#define HIFN_CRYPT_CMD_ALG_DES 0x0000 /* DES */
|
||||
#define HIFN_CRYPT_CMD_ALG_3DES 0x0001 /* 3DES */
|
||||
#define HIFN_CRYPT_CMD_ALG_RC4 0x0002 /* RC4 */
|
||||
#define HIFN_CRYPT_CMD_MODE_MASK 0x0018 /* DES mode: */
|
||||
#define HIFN_CRYPT_CMD_ALG_AES 0x0003 /* AES */
|
||||
#define HIFN_CRYPT_CMD_MODE_MASK 0x0018 /* Encrypt mode: */
|
||||
#define HIFN_CRYPT_CMD_MODE_ECB 0x0000 /* ECB */
|
||||
#define HIFN_CRYPT_CMD_MODE_CBC 0x0008 /* CBC */
|
||||
#define HIFN_CRYPT_CMD_MODE_CFB 0x0010 /* CFB */
|
||||
|
|
@ -420,6 +429,11 @@ typedef struct hifn_crypt_command {
|
|||
#define HIFN_CRYPT_CMD_SRCLEN_M 0xc000
|
||||
#define HIFN_CRYPT_CMD_SRCLEN_S 14
|
||||
|
||||
#define HIFN_CRYPT_CMD_KSZ_MASK 0x0600 /* AES key size: */
|
||||
#define HIFN_CRYPT_CMD_KSZ_128 0x0000 /* 128 bit */
|
||||
#define HIFN_CRYPT_CMD_KSZ_192 0x0200 /* 192 bit */
|
||||
#define HIFN_CRYPT_CMD_KSZ_256 0x0400 /* 256 bit */
|
||||
|
||||
/*
|
||||
* Structure to help build up the command data structure.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -67,6 +67,8 @@
|
|||
#define HIFN_3DES_KEY_LENGTH 24
|
||||
#define HIFN_MAX_CRYPT_KEY_LENGTH HIFN_3DES_KEY_LENGTH
|
||||
#define HIFN_IV_LENGTH 8
|
||||
#define HIFN_AES_IV_LENGTH 16
|
||||
#define HIFN_MAX_IV_LENGTH HIFN_AES_IV_LENGTH
|
||||
|
||||
/*
|
||||
* Length values for authentication
|
||||
|
|
@ -111,7 +113,7 @@ struct hifn_dma {
|
|||
struct hifn_session {
|
||||
int hs_state;
|
||||
int hs_prev_op; /* XXX collapse into hs_flags? */
|
||||
u_int8_t hs_iv[HIFN_IV_LENGTH];
|
||||
u_int8_t hs_iv[HIFN_MAX_IV_LENGTH];
|
||||
};
|
||||
|
||||
#define HIFN_RING_SYNC(sc, r, i, f) \
|
||||
|
|
@ -166,7 +168,9 @@ struct hifn_softc {
|
|||
int sc_flags;
|
||||
#define HIFN_HAS_RNG 0x1 /* includes random number generator */
|
||||
#define HIFN_HAS_PUBLIC 0x2 /* includes public key support */
|
||||
#define HIFN_IS_7811 0x4 /* Hifn 7811 part */
|
||||
#define HIFN_HAS_AES 0x4 /* includes AES support */
|
||||
#define HIFN_IS_7811 0x8 /* Hifn 7811 part */
|
||||
#define HIFN_IS_7956 0x10 /* Hifn 7956/7955 don't have SDRAM */
|
||||
struct callout sc_rngto; /* for polling RNG */
|
||||
struct callout sc_tickto; /* for managing DMA */
|
||||
int sc_rngfirst;
|
||||
|
|
@ -266,7 +270,7 @@ struct hifn_operand {
|
|||
struct hifn_command {
|
||||
u_int16_t session_num;
|
||||
u_int16_t base_masks, cry_masks, mac_masks;
|
||||
u_int8_t iv[HIFN_IV_LENGTH], *ck, mac[HIFN_MAC_KEY_LENGTH];
|
||||
u_int8_t iv[HIFN_MAX_IV_LENGTH], *ck, mac[HIFN_MAC_KEY_LENGTH];
|
||||
int cklen;
|
||||
int sloplen, slopidx;
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue