mirror of
https://github.com/freebsd/freebsd-src
synced 2024-10-17 13:53:39 +00:00
Put this old tool for dumping PCI expansion ROM images somewhere useful.
WARNING: THIS IS NOT STABLE ON NON-I386 ARCHITECTURES, AND NEEDS SPECIFIC KNOWLEDGE OF THE ADDRESS SPACE ON YOUR SYSTEM TO WORK.
This commit is contained in:
Bruce M Simpson
parent
dcc76067cd
commit
14dd02e134
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=167167
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@ -43,6 +43,7 @@ mfc Merge a directory from HEAD to a branch where it does not
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mid Create a Message-ID database for mailing lists.
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ncpus Count the number of processors
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pciid Generate src/share/misc/pci_vendors.
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pciroms A tool for dumping PCI ROM images. WARNING: alpha quality.
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pirtool A tool for dumping the $PIR table on i386 machines at runtime.
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portsinfo Generate list of new ports for last two weeks.
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prstats Generate statistics about the PR database.
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10
tools/tools/pciroms/Makefile
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10
tools/tools/pciroms/Makefile
Normal file
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@ -0,0 +1,10 @@
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#
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# $FreeBSD$
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#
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PROG= pciroms
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NO_MAN=
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WARNS?= 6
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.include <bsd.prog.mk>
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411
tools/tools/pciroms/pciroms.c
Normal file
411
tools/tools/pciroms/pciroms.c
Normal file
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@ -0,0 +1,411 @@
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/*
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* Copyright (c) 2007 Bruce M. Simpson.
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* All rights reserved
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Bruce M. Simpson.
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* 4. Neither the name of Bruce M. Simpson nor the names of
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY BRUCE M. SIMPSON AND AFFILIATES
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/types.h>
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#include <sys/ioctl.h>
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#include <sys/pciio.h>
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#include <sys/mman.h>
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#include <sys/memrange.h>
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#include <sys/stat.h>
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#include <machine/endian.h>
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#include <stddef.h>
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#include <inttypes.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <libgen.h>
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#include <fcntl.h>
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#include <string.h>
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#include <unistd.h>
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#define _PATH_DEVPCI "/dev/pci"
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#define _PATH_DEVMEM "/dev/mem"
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#define PCI_CFG_CMD 0x04 /* command register */
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#define PCI_CFG_ROM_BAR 0x30 /* rom base register */
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#define PCI_ROM_ADDR_MASK 0xFFFFFC00 /* the 21 MSBs form the BAR */
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#define PCI_ROM_RESERVED_MASK 0x03FE /* mask for reserved bits */
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#define PCI_ROM_ACTIVATE 0x01 /* mask for activation bit */
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#define PCI_CMD_MEM_SPACE 0x02 /* memory space bit */
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#define PCI_HDRTYPE_MFD 0x80 /* MFD bit in HDRTYPE reg. */
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#define MAX_PCI_DEVS 64 /* # of devices in system */
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typedef enum {
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PRINT = 0,
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SAVE = 1
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} action_t;
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/*
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* This is set to a safe physical base address in PCI range for my Vaio.
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* YOUR MACHINE *WILL* VARY, I SUGGEST YOU LOOK UP YOUR MACHINE'S MEMORY
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* MAP IN DETAIL IF YOU PLAN ON SAVING ROMS.
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*
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* This is the hole between the APIC and the BIOS (FED00000-FEDFFFFF);
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* should be a safe range on the i815 Solano chipset.
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*/
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#define PCI_DEFAULT_ROM_ADDR 0xFED00000
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static char *progname = NULL;
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static uintptr_t base_addr = PCI_DEFAULT_ROM_ADDR;
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static void usage(void);
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static void banner(void);
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static void pci_enum_devs(int pci_fd, action_t action);
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static uint32_t pci_testrombar(int pci_fd, struct pci_conf *dev);
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static int pci_enable_bars(int pci_fd, struct pci_conf *dev,
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uint16_t *oldcmd);
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static int pci_disable_bars(int pci_fd, struct pci_conf *dev,
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uint16_t *oldcmd);
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static int pci_save_rom(char *filename, int romsize);
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int
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main(int argc, char *argv[])
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{
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int pci_fd;
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int err;
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int ch;
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action_t action;
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char *base_addr_string;
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char *ep;
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err = -1;
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pci_fd = -1;
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action = PRINT;
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base_addr_string = NULL;
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ep = NULL;
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progname = basename(argv[0]);
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while ((ch = getopt(argc, argv, "sb:h")) != -1)
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switch (ch) {
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case 's':
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action = SAVE;
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break;
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case 'b':
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base_addr_string = optarg;
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break;
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case 'h':
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default:
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usage();
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}
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argc -= optind;
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argv += optind;
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if (base_addr_string != NULL) {
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uintmax_t base_addr_max;
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base_addr_max = strtoumax(base_addr_string, &ep, 16);
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if (*ep != '\0') {
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fprintf(stderr, "Invalid base address.\r\n");
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usage();
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}
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/* XXX: TODO: deal with 64-bit PCI. */
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base_addr = (uintptr_t)base_addr_max;
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base_addr &= ~PCI_ROM_RESERVED_MASK;
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}
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if (argc > 0)
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usage();
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if ((pci_fd = open(_PATH_DEVPCI, O_RDWR)) == -1) {
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perror("open");
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goto cleanup;
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}
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banner();
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pci_enum_devs(pci_fd, action);
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err = 0;
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cleanup:
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if (pci_fd != -1)
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close(pci_fd);
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exit ((err == 0) ? EXIT_SUCCESS : EXIT_FAILURE);
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}
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static void
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usage(void)
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{
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fprintf(stderr, "usage: %s [-s] [-b <base-address>]\r\n", progname);
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exit(EXIT_FAILURE);
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}
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static void
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banner(void)
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{
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fprintf(stderr,
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"WARNING: You are advised to run this program in single\r\n"
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"user mode, with few or no processes running.\r\n\r\n");
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}
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/*
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* Enumerate PCI device list to a limit of MAX_PCI_DEVS devices.
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*/
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static void
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pci_enum_devs(int pci_fd, action_t action)
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{
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struct pci_conf devs[MAX_PCI_DEVS];
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char filename[16];
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struct pci_conf_io pc;
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struct pci_conf *p;
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int result;
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int romsize;
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uint16_t oldcmd;
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result = -1;
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romsize = 0;
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bzero(&pc, sizeof(pc));
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pc.match_buf_len = sizeof(devs);
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pc.matches = devs;
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if (ioctl(pci_fd, PCIOCGETCONF, &pc) == -1) {
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perror("ioctl PCIOCGETCONF");
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return;
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}
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if (pc.status == PCI_GETCONF_ERROR) {
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fprintf(stderr,
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"Error fetching PCI device list from kernel.\r\n");
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return;
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}
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if (pc.status == PCI_GETCONF_MORE_DEVS) {
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fprintf(stderr,
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"More than %d devices exist. Only the first %d will be inspected.\r\n",
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MAX_PCI_DEVS, MAX_PCI_DEVS);
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}
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for (p = devs ; p < &devs[pc.num_matches]; p++) {
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/* No PCI bridges; only PCI devices. */
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if (p->pc_hdr != 0x00)
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continue;
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romsize = pci_testrombar(pci_fd, p);
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switch (action) {
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case PRINT:
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printf("Bus %02Xh Device %02Xh Function %02Xh: ",
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p->pc_sel.pc_bus, p->pc_sel.pc_dev,
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p->pc_sel.pc_func);
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printf((romsize ? "%dKB ROM aperture detected."
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: "No ROM present."), romsize/1024);
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printf("\r\n");
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break;
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case SAVE:
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if (romsize == 0)
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continue; /* XXX */
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snprintf(filename, sizeof(filename), "%08X.rom",
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((p->pc_device << 16) | p->pc_vendor));
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fprintf(stderr, "Saving %dKB ROM image to %s...\r\n",
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romsize, filename);
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if (pci_enable_bars(pci_fd, p, &oldcmd) == 0)
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result = pci_save_rom(filename, romsize);
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pci_disable_bars(pci_fd, p, &oldcmd);
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if (result == 0) {
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fprintf(stderr, "Done.\r\n");
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} else {
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fprintf(stderr,
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"An error occurred whilst saving the ROM.\r\n");
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}
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break;
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} /* switch */
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} /* for */
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}
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/*
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* Return: size of ROM aperture off dev, 0 if no ROM exists.
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*/
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static uint32_t
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pci_testrombar(int pci_fd, struct pci_conf *dev)
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{
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struct pci_io io;
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uint32_t romsize;
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romsize = 0;
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/*
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* Only attempt to discover ROMs on Header Type 0x00 devices.
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*/
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if (dev->pc_hdr != 0x00)
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return romsize;
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/*
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* Activate ROM BAR
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*/
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io.pi_sel = dev->pc_sel;
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io.pi_reg = PCI_CFG_ROM_BAR;
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io.pi_width = 4;
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io.pi_data = 0xFFFFFFFF;
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if (ioctl(pci_fd, PCIOCWRITE, &io) == -1)
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return romsize;
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/*
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* Read back ROM BAR and compare with mask
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*/
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if (ioctl(pci_fd, PCIOCREAD, &io) == -1)
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return 0;
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/*
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* Calculate ROM aperture if one was set.
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*/
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if (io.pi_data & PCI_ROM_ADDR_MASK)
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romsize = -(io.pi_data & PCI_ROM_ADDR_MASK);
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/*
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* Disable the ROM BAR when done.
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*/
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io.pi_data = 0;
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if (ioctl(pci_fd, PCIOCWRITE, &io) == -1)
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return 0;
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return romsize;
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}
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static int
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pci_save_rom(char *filename, int romsize)
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{
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int fd, mem_fd, err;
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void *map_addr;
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fd = err = mem_fd = -1;
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map_addr = MAP_FAILED;
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if ((mem_fd = open(_PATH_DEVMEM, O_RDONLY)) == -1) {
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perror("open");
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return -1;
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}
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map_addr = mmap(NULL, romsize, PROT_READ, MAP_SHARED|MAP_NOCORE,
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mem_fd, base_addr);
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/* Dump ROM aperture to a file. */
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if ((fd = open(filename, O_CREAT|O_RDWR|O_TRUNC|O_NOFOLLOW,
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S_IRUSR|S_IWUSR)) == -1) {
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perror("open");
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goto cleanup;
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}
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if (write(fd, map_addr, romsize) != romsize)
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perror("write");
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err = 0;
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cleanup:
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if (fd != -1)
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close(fd);
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if (map_addr != MAP_FAILED)
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munmap((void *)base_addr, romsize);
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if (mem_fd != -1)
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close(mem_fd);
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return err;
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}
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static int
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pci_enable_bars(int pci_fd, struct pci_conf *dev, uint16_t *oldcmd)
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{
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struct pci_io io;
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/* Don't grok bridges. */
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if (dev->pc_hdr != 0x00)
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return -1;
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/* Save command register. */
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io.pi_sel = dev->pc_sel;
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io.pi_reg = PCI_CFG_CMD;
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io.pi_width = 2;
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if (ioctl(pci_fd, PCIOCREAD, &io) == -1)
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return -1;
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*oldcmd = (uint16_t)io.pi_data;
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io.pi_data |= PCI_CMD_MEM_SPACE;
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if (ioctl(pci_fd, PCIOCWRITE, &io) == -1)
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return -1;
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/*
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* Activate ROM BAR and map at the specified base address.
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*/
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io.pi_sel = dev->pc_sel;
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io.pi_reg = PCI_CFG_ROM_BAR;
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io.pi_width = 4;
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io.pi_data = (base_addr | PCI_ROM_ACTIVATE);
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if (ioctl(pci_fd, PCIOCWRITE, &io) == -1)
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return -1;
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return 0;
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}
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static int
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pci_disable_bars(int pci_fd, struct pci_conf *dev, uint16_t *oldcmd)
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{
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struct pci_io io;
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/*
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* Clear ROM BAR to deactivate the mapping.
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*/
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io.pi_sel = dev->pc_sel;
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io.pi_reg = PCI_CFG_ROM_BAR;
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io.pi_width = 4;
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io.pi_data = 0;
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if (ioctl(pci_fd, PCIOCWRITE, &io) == -1)
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return 0;
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/*
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* Restore state of the command register.
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*/
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io.pi_sel = dev->pc_sel;
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io.pi_reg = PCI_CFG_CMD;
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io.pi_width = 2;
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io.pi_data = *oldcmd;
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if (ioctl(pci_fd, PCIOCWRITE, &io) == -1) {
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perror("ioctl");
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return 0;
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}
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return 0;
|
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}
|
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