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Add the new armv7 architecture.

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This commit is contained in:
Warner Losh 2018-01-31 23:16:19 +00:00
parent 0d37a428f0
commit 13368c3830
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=328645
1 changed files with 7 additions and 0 deletions
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7
share/man/man7/arch.7
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@ -95,6 +95,7 @@ architectures, the final release.
.It arm Ta 6.0
.It armeb Ta 8.0
.It armv6 Ta 10.0
.It armv7 Ta 12.0
.It arm64 Ta 11.0
.It ia64 Ta 5.0 Ta 10.x
.It i386 Ta 1.0
@ -164,6 +165,8 @@ Examples are:
.Dv arm64
currently does not support execution of
.Dv armv6
or
.Dv armv7
binaries, even if the CPU implements
.Dv AArch32
execution state.
@ -220,6 +223,7 @@ is 8 bytes on all supported architectures except i386.
.It arm Ta little Ta unsigned
.It armeb Ta big Ta unsigned
.It armv6 Ta little Ta unsigned
.It armv7 Ta little Ta unsigned
.It arm64 Ta little Ta unsigned
.It i386 Ta little Ta signed
.It mips Ta big Ta signed
@ -245,6 +249,7 @@ is 8 bytes on all supported architectures except i386.
.It arm Ta 4K
.It armeb Ta 4K
.It armv6 Ta 4K, 1M
.It armv7 Ta 4K, 1M
.It arm64 Ta 4K, 2M, 1G
.It i386 Ta 4K, 2M (PAE), 4M
.It mips Ta 4K
@ -270,6 +275,7 @@ is 8 bytes on all supported architectures except i386.
.It arm Ta soft Ta soft, double precision
.It armeb Ta soft Ta soft, double precision
.It armv6 Ta hard(1) Ta hard, double precision
.It armv7 Ta hard(1) Ta hard, double precision
.It arm64 Ta hard Ta soft, quad precision
.It i386 Ta hard Ta hard, 80 bit
.It mips Ta soft Ta identical to double
@ -322,6 +328,7 @@ Architecture-specific macros:
.It arm Ta Dv __arm__
.It armeb Ta Dv __arm__
.It armv6 Ta Dv __arm__, Dv __ARM_ARCH >= 6
.It armv7 Ta Dv __arm__, Dv __ARM_ARCH >= 7
.It arm64 Ta Dv __aarch64__
.It i386 Ta Dv __i386__
.It mips Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_o32