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x86: Add defines for workaround bits in AMD's MSR "Decode Configuration"

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They are a bit more informative than raw hexadecimal values.

While here, sort existing defines of bits for AMD MSRs to match the address
order.

Reviewed by:	kib, emaste
Sponsored by:   The FreeBSD Foundation
Differential Revision:	https://reviews.freebsd.org/D41816
This commit is contained in:
Olivier Certner 2023-09-11 15:10:35 +02:00 committed by Ed Maste
parent 74be676d87
commit 125bbadf60
2 changed files with 10 additions and 4 deletions
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5
sys/amd64/amd64/initcpu.c
View file

@ -101,7 +101,8 @@ init_amd(void)
case 0x10:
case 0x12:
if ((cpu_feature2 & CPUID2_HV) == 0)
wrmsr(MSR_DE_CFG, rdmsr(MSR_DE_CFG) | 1);
wrmsr(MSR_DE_CFG, rdmsr(MSR_DE_CFG) |
DE_CFG_10H_12H_STACK_POINTER_JUMP_FIX_BIT);
break;
}
@ -151,7 +152,7 @@ init_amd(void)
(cpu_feature2 & CPUID2_HV) == 0) {
/* 1021 */
msr = rdmsr(MSR_DE_CFG);
msr |= 0x2000;
msr |= DE_CFG_ZEN_LOAD_STALE_DATA_FIX_BIT;
wrmsr(MSR_DE_CFG, msr);
/* 1033 */

9
sys/x86/include/specialreg.h
View file

@ -1162,11 +1162,16 @@
#define MSR_IC_CFG 0xc0011021 /* Instruction Cache Configuration */
#define MSR_DE_CFG 0xc0011029 /* Decode Configuration */
/* MSR_AMDK8_IPM */
#define AMDK8_SMIONCMPHALT (1ULL << 27)
#define AMDK8_C1EONCMPHALT (1ULL << 28)
/* MSR_VM_CR related */
#define VM_CR_SVMDIS 0x10 /* SVM: disabled by BIOS */
#define AMDK8_SMIONCMPHALT (1ULL << 27)
#define AMDK8_C1EONCMPHALT (1ULL << 28)
/* MSR_DE_CFG */
#define DE_CFG_10H_12H_STACK_POINTER_JUMP_FIX_BIT 0x1
#define DE_CFG_ZEN_LOAD_STALE_DATA_FIX_BIT 0x2000
/* VIA ACE crypto featureset: for via_feature_rng */
#define VIA_HAS_RNG 1 /* cpu has RNG */