mirror of
https://github.com/freebsd/freebsd-src
synced 2024-09-29 13:15:05 +00:00
We use the stock version of this file now.
I folded our rev 1.2 localizations into the FSF/GNU tree.
This commit is contained in:
parent
8f29d50bf5
commit
098e7024f7
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=77312
|
@ -1,5 +1,5 @@
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|||
/* tc-i386.h -- Header file for tc-i386.c
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Copyright (C) 1989, 92, 93, 94, 95, 96, 97, 98, 99, 2000
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Copyright (C) 1989, 92, 93, 94, 95, 96, 97, 98, 99, 2000, 2001
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Free Software Foundation.
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This file is part of GAS, the GNU Assembler.
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@ -19,8 +19,10 @@
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|||
Software Foundation, 59 Temple Place - Suite 330, Boston, MA
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02111-1307, USA. */
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/* $FreeBSD$ */
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#ifndef TC_I386
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#define TC_I386 1
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@ -43,21 +45,25 @@ struct fix;
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#define tc_fix_adjustable(X) tc_i386_fix_adjustable(X)
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extern int tc_i386_fix_adjustable PARAMS ((struct fix *));
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/* This is the relocation type for direct references to GLOBAL_OFFSET_TABLE.
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* It comes up in complicated expressions such as
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* _GLOBAL_OFFSET_TABLE_+[.-.L284], which cannot be expressed normally with
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* the regular expressions. The fixup specified here when used at runtime
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* implies that we should add the address of the GOT to the specified location,
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* and as a result we have simplified the expression into something we can use.
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*/
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#define TC_RELOC_GLOBAL_OFFSET_TABLE BFD_RELOC_386_GOTPC
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#if (defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) || defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)) && !defined (TE_PE)
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/* This arranges for gas/write.c to not apply a relocation if
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tc_fix_adjustable() says it is not adjustable.
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The "! symbol_used_in_reloc_p" test is there specifically to cover
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the case of non-global symbols in linkonce sections. It's the
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generally correct thing to do though; If a reloc is going to be
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emitted against a symbol then we don't want to adjust the fixup by
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applying the reloc during assembly. The reloc will be applied by
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the linker during final link. */
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#define TC_FIX_ADJUSTABLE(fixP) \
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(! symbol_used_in_reloc_p ((fixP)->fx_addsy) && tc_fix_adjustable (fixP))
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#endif
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/* This expression evaluates to false if the relocation is for a local object
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for which we still want to do the relocation at runtime. True if we
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are willing to perform this relocation while building the .o file.
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This is only used for pcrel relocations, so GOTOFF does not need to be
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checked here. I am not sure if some of the others are ever used with
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pcrel, but it is easier to be safe than sorry. */
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pcrel, but it is easier to be safe than sorry. */
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#define TC_RELOC_RTSYM_LOC_FIXUP(FIX) \
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((FIX)->fx_r_type != BFD_RELOC_386_PLT32 \
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@ -70,6 +76,8 @@ extern int tc_i386_fix_adjustable PARAMS ((struct fix *));
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&& ! S_IS_COMMON ((FIX)->fx_addsy))))
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#define TARGET_ARCH bfd_arch_i386
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#define TARGET_MACH (i386_mach ())
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extern unsigned long i386_mach PARAMS ((void));
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#ifdef TE_FreeBSD
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#define AOUT_TARGET_FORMAT "a.out-i386-freebsd"
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@ -93,9 +101,8 @@ extern int tc_i386_fix_adjustable PARAMS ((struct fix *));
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#define AOUT_TARGET_FORMAT "a.out-i386"
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#endif
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#if ((defined (OBJ_MAYBE_ELF) && defined (OBJ_MAYBE_COFF)) \
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|| (defined (OBJ_MAYBE_ELF) && defined (OBJ_MAYBE_AOUT)) \
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|| (defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)))
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#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
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|| defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
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extern const char *i386_target_format PARAMS ((void));
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#define TARGET_FORMAT i386_target_format ()
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#else
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@ -139,7 +146,6 @@ extern int tc_coff_sizemachdep PARAMS ((fragS *frag));
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/* Need this for PIC relocations */
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#define NEED_FX_R_TYPE
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#ifdef TE_386BSD
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/* The BSDI linker apparently rejects objects with a machine type of
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M_386 (100). */
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@ -189,13 +195,14 @@ extern const char extra_symbol_chars[];
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/* Prefixes will be emitted in the order defined below.
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WAIT_PREFIX must be the first prefix since FWAIT is really is an
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instruction, and so must come before any prefixes. */
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instruction, and so must come before any prefixes. */
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#define WAIT_PREFIX 0
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#define LOCKREP_PREFIX 1
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#define ADDR_PREFIX 2
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#define DATA_PREFIX 3
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#define SEG_PREFIX 4
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#define MAX_PREFIXES 5 /* max prefixes per opcode */
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#define REX_PREFIX 5 /* must come last. */
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#define MAX_PREFIXES 6 /* max prefixes per opcode */
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/* we define the syntax here (modulo base,index,scale syntax) */
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#define REGISTER_PREFIX '%'
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@ -222,10 +229,9 @@ extern const char extra_symbol_chars[];
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#define BYTE_MNEM_SUFFIX 'b'
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#define SHORT_MNEM_SUFFIX 's'
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#define LONG_MNEM_SUFFIX 'l'
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#define QWORD_MNEM_SUFFIX 'q'
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/* Intel Syntax */
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#define LONG_DOUBLE_MNEM_SUFFIX 'x'
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/* Intel Syntax */
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#define DWORD_MNEM_SUFFIX 'd'
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/* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */
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#define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */
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@ -244,77 +250,6 @@ extern const char extra_symbol_chars[];
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#define OFFSET_FLAT 6
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#define FLAT 7
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#define NONE_FOUND 8
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/*
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When an operand is read in it is classified by its type. This type includes
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all the possible ways an operand can be used. Thus, '%eax' is both 'register
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# 0' and 'The Accumulator'. In our language this is expressed by OR'ing
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'Reg32' (any 32 bit register) and 'Acc' (the accumulator).
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Operands are classified so that we can match given operand types with
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the opcode table in opcode/i386.h.
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*/
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/* register */
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#define Reg8 0x1 /* 8 bit reg */
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#define Reg16 0x2 /* 16 bit reg */
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#define Reg32 0x4 /* 32 bit reg */
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/* immediate */
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#define Imm8 0x8 /* 8 bit immediate */
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#define Imm8S 0x10 /* 8 bit immediate sign extended */
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#define Imm16 0x20 /* 16 bit immediate */
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#define Imm32 0x40 /* 32 bit immediate */
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#define Imm1 0x80 /* 1 bit immediate */
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/* memory */
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#define BaseIndex 0x100
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/* Disp8,16,32 are used in different ways, depending on the
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instruction. For jumps, they specify the size of the PC relative
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displacement, for baseindex type instructions, they specify the
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size of the offset relative to the base register, and for memory
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offset instructions such as `mov 1234,%al' they specify the size of
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the offset relative to the segment base. */
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#define Disp8 0x200 /* 8 bit displacement */
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#define Disp16 0x400 /* 16 bit displacement */
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#define Disp32 0x800 /* 32 bit displacement */
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/* specials */
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#define InOutPortReg 0x1000 /* register to hold in/out port addr = dx */
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#define ShiftCount 0x2000 /* register to hold shift cound = cl */
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#define Control 0x4000 /* Control register */
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#define Debug 0x8000 /* Debug register */
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#define Test 0x10000 /* Test register */
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#define FloatReg 0x20000 /* Float register */
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#define FloatAcc 0x40000 /* Float stack top %st(0) */
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#define SReg2 0x80000 /* 2 bit segment register */
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#define SReg3 0x100000 /* 3 bit segment register */
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#define Acc 0x200000 /* Accumulator %al or %ax or %eax */
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#define JumpAbsolute 0x400000
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#define RegMMX 0x800000 /* MMX register */
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#define RegXMM 0x1000000 /* XMM registers in PIII */
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#define EsSeg 0x2000000 /* String insn operand with fixed es segment */
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/* InvMem is for instructions with a modrm byte that only allow a
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general register encoding in the i.tm.mode and i.tm.regmem fields,
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eg. control reg moves. They really ought to support a memory form,
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but don't, so we add an InvMem flag to the register operand to
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indicate that it should be encoded in the i.tm.regmem field. */
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#define InvMem 0x4000000
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#define Reg (Reg8|Reg16|Reg32) /* gen'l register */
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#define WordReg (Reg16|Reg32)
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#define ImplicitRegister (InOutPortReg|ShiftCount|Acc|FloatAcc)
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#define Imm (Imm8|Imm8S|Imm16|Imm32) /* gen'l immediate */
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#define Disp (Disp8|Disp16|Disp32) /* General displacement */
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#define AnyMem (Disp|BaseIndex|InvMem) /* General memory */
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/* The following aliases are defined because the opcode table
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carefully specifies the allowed memory types for each instruction.
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At the moment we can only tell a memory reference size by the
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instruction suffix, so there's not much point in defining Mem8,
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Mem16, Mem32 and Mem64 opcode modifiers - We might as well just use
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the suffix directly to check memory operands. */
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#define LLongMem AnyMem /* 64 bits (or more) */
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#define LongMem AnyMem /* 32 bit memory ref */
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#define ShortMem AnyMem /* 16 bit memory ref */
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#define WordMem AnyMem /* 16 or 32 bit memory ref */
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#define ByteMem AnyMem /* 8 bit memory ref */
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#define SMALLEST_DISP_TYPE(num) \
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(fits_in_signed_byte(num) ? (Disp8|Disp32) : Disp32)
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typedef struct
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{
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@ -333,7 +268,33 @@ typedef struct
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AMD 3DNow! instructions.
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If this template has no extension opcode (the usual case) use None */
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unsigned int extension_opcode;
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#define None 0xffff /* If no extension_opcode is possible. */
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#define None 0xffff /* If no extension_opcode is possible. */
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/* cpu feature flags */
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unsigned int cpu_flags;
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#define Cpu086 0x1 /* Any old cpu will do, 0 does the same */
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#define Cpu186 0x2 /* i186 or better required */
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#define Cpu286 0x4 /* i286 or better required */
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#define Cpu386 0x8 /* i386 or better required */
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#define Cpu486 0x10 /* i486 or better required */
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#define Cpu586 0x20 /* i585 or better required */
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#define Cpu686 0x40 /* i686 or better required */
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#define CpuP4 0x80 /* Pentium4 or better required */
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#define CpuK6 0x100 /* AMD K6 or better required*/
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#define CpuAthlon 0x200 /* AMD Athlon or better required*/
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#define CpuSledgehammer 0x400 /* Sledgehammer or better required */
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#define CpuMMX 0x800 /* MMX support required */
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#define CpuSSE 0x1000 /* Streaming SIMD extensions required */
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#define CpuSSE2 0x2000 /* Streaming SIMD extensions 2 required */
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#define Cpu3dnow 0x4000 /* 3dnow! support required */
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#define CpuUnknown 0x8000 /* The CPU is unknown, be on the safe side. */
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/* These flags are set by gas depending on the flag_code. */
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#define Cpu64 0x4000000 /* 64bit support required */
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#define CpuNo64 0x8000000 /* Not supported in the 64bit mode */
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/* The default value for unknown CPUs - enable all features to avoid problems. */
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#define CpuUnknownFlags (Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuSledgehammer|CpuMMX|CpuSSE|CpuSSE2|Cpu3dnow|CpuK6|CpuAthlon)
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/* the bits in opcode_modifier are used to generate the final opcode from
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the base_opcode. These bits also are used to detect alternate forms of
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@ -349,35 +310,107 @@ typedef struct
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|||
#define FloatR 0x8 /* src/dest swap for floats: MUST BE 0x8 */
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#define ShortForm 0x10 /* register is in low 3 bits of opcode */
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#define FloatMF 0x20 /* FP insn memory format bit, sized by 0x4 */
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#define Jump 0x40 /* special case for jump insns. */
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#define Jump 0x40 /* special case for jump insns. */
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#define JumpDword 0x80 /* call and jump */
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#define JumpByte 0x100 /* loop and jecxz */
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#define JumpInterSegment 0x200 /* special case for intersegment leaps/calls */
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#define FloatD 0x400 /* direction for float insns: MUST BE 0x400 */
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#define Seg2ShortForm 0x800 /* encoding of load segment reg insns */
|
||||
#define Seg3ShortForm 0x1000 /* fs/gs segment register insns. */
|
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#define Seg3ShortForm 0x1000 /* fs/gs segment register insns. */
|
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#define Size16 0x2000 /* needs size prefix if in 32-bit mode */
|
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#define Size32 0x4000 /* needs size prefix if in 16-bit mode */
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#define IgnoreSize 0x8000 /* instruction ignores operand size prefix */
|
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#define DefaultSize 0x10000 /* default insn size depends on mode */
|
||||
#define No_bSuf 0x20000 /* b suffix on instruction illegal */
|
||||
#define No_wSuf 0x40000 /* w suffix on instruction illegal */
|
||||
#define No_lSuf 0x80000 /* l suffix on instruction illegal */
|
||||
#define No_sSuf 0x100000 /* s suffix on instruction illegal */
|
||||
#define No_dSuf 0x200000 /* d suffix on instruction illegal */
|
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#define No_xSuf 0x400000 /* x suffix on instruction illegal */
|
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#define FWait 0x800000 /* instruction needs FWAIT */
|
||||
#define IsString 0x1000000 /* quick test for string instructions */
|
||||
#define regKludge 0x2000000 /* fake an extra reg operand for clr, imul */
|
||||
#define IsPrefix 0x4000000 /* opcode is a prefix */
|
||||
#define ImmExt 0x8000000 /* instruction has extension in 8 bit imm */
|
||||
#define Size64 0x8000 /* needs size prefix if in 16-bit mode */
|
||||
#define IgnoreSize 0x10000 /* instruction ignores operand size prefix */
|
||||
#define DefaultSize 0x20000 /* default insn size depends on mode */
|
||||
#define No_bSuf 0x40000 /* b suffix on instruction illegal */
|
||||
#define No_wSuf 0x80000 /* w suffix on instruction illegal */
|
||||
#define No_lSuf 0x100000 /* l suffix on instruction illegal */
|
||||
#define No_sSuf 0x200000 /* s suffix on instruction illegal */
|
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#define No_qSuf 0x400000 /* q suffix on instruction illegal */
|
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#define No_xSuf 0x800000 /* x suffix on instruction illegal */
|
||||
#define FWait 0x1000000 /* instruction needs FWAIT */
|
||||
#define IsString 0x2000000 /* quick test for string instructions */
|
||||
#define regKludge 0x4000000 /* fake an extra reg operand for clr, imul */
|
||||
#define IsPrefix 0x8000000 /* opcode is a prefix */
|
||||
#define ImmExt 0x10000000 /* instruction has extension in 8 bit imm */
|
||||
#define NoRex64 0x20000000 /* instruction don't need Rex64 prefix. */
|
||||
#define Rex64 0x40000000 /* instruction require Rex64 prefix. */
|
||||
#define Ugh 0x80000000 /* deprecated fp insn, gets a warning */
|
||||
|
||||
/* operand_types[i] describes the type of operand i. This is made
|
||||
by OR'ing together all of the possible type masks. (e.g.
|
||||
'operand_types[i] = Reg|Imm' specifies that operand i can be
|
||||
either a register or an immediate operand */
|
||||
either a register or an immediate operand. */
|
||||
unsigned int operand_types[3];
|
||||
|
||||
/* operand_types[i] bits */
|
||||
/* register */
|
||||
#define Reg8 0x1 /* 8 bit reg */
|
||||
#define Reg16 0x2 /* 16 bit reg */
|
||||
#define Reg32 0x4 /* 32 bit reg */
|
||||
#define Reg64 0x8 /* 64 bit reg */
|
||||
/* immediate */
|
||||
#define Imm8 0x10 /* 8 bit immediate */
|
||||
#define Imm8S 0x20 /* 8 bit immediate sign extended */
|
||||
#define Imm16 0x40 /* 16 bit immediate */
|
||||
#define Imm32 0x80 /* 32 bit immediate */
|
||||
#define Imm32S 0x100 /* 32 bit immediate sign extended */
|
||||
#define Imm64 0x200 /* 64 bit immediate */
|
||||
#define Imm1 0x400 /* 1 bit immediate */
|
||||
/* memory */
|
||||
#define BaseIndex 0x800
|
||||
/* Disp8,16,32 are used in different ways, depending on the
|
||||
instruction. For jumps, they specify the size of the PC relative
|
||||
displacement, for baseindex type instructions, they specify the
|
||||
size of the offset relative to the base register, and for memory
|
||||
offset instructions such as `mov 1234,%al' they specify the size of
|
||||
the offset relative to the segment base. */
|
||||
#define Disp8 0x1000 /* 8 bit displacement */
|
||||
#define Disp16 0x2000 /* 16 bit displacement */
|
||||
#define Disp32 0x4000 /* 32 bit displacement */
|
||||
#define Disp32S 0x8000 /* 32 bit signed displacement */
|
||||
#define Disp64 0x10000 /* 64 bit displacement */
|
||||
/* specials */
|
||||
#define InOutPortReg 0x20000 /* register to hold in/out port addr = dx */
|
||||
#define ShiftCount 0x40000 /* register to hold shift cound = cl */
|
||||
#define Control 0x80000 /* Control register */
|
||||
#define Debug 0x100000 /* Debug register */
|
||||
#define Test 0x200000 /* Test register */
|
||||
#define FloatReg 0x400000 /* Float register */
|
||||
#define FloatAcc 0x800000 /* Float stack top %st(0) */
|
||||
#define SReg2 0x1000000 /* 2 bit segment register */
|
||||
#define SReg3 0x2000000 /* 3 bit segment register */
|
||||
#define Acc 0x4000000 /* Accumulator %al or %ax or %eax */
|
||||
#define JumpAbsolute 0x8000000
|
||||
#define RegMMX 0x10000000 /* MMX register */
|
||||
#define RegXMM 0x20000000 /* XMM registers in PIII */
|
||||
#define EsSeg 0x40000000 /* String insn operand with fixed es segment */
|
||||
|
||||
/* InvMem is for instructions with a modrm byte that only allow a
|
||||
general register encoding in the i.tm.mode and i.tm.regmem fields,
|
||||
eg. control reg moves. They really ought to support a memory form,
|
||||
but don't, so we add an InvMem flag to the register operand to
|
||||
indicate that it should be encoded in the i.tm.regmem field. */
|
||||
#define InvMem 0x80000000
|
||||
|
||||
#define Reg (Reg8|Reg16|Reg32|Reg64) /* gen'l register */
|
||||
#define WordReg (Reg16|Reg32|Reg64)
|
||||
#define ImplicitRegister (InOutPortReg|ShiftCount|Acc|FloatAcc)
|
||||
#define Imm (Imm8|Imm8S|Imm16|Imm32S|Imm32|Imm64) /* gen'l immediate */
|
||||
#define EncImm (Imm8|Imm16|Imm32|Imm32S) /* Encodable gen'l immediate */
|
||||
#define Disp (Disp8|Disp16|Disp32|Disp32S|Disp64) /* General displacement */
|
||||
#define AnyMem (Disp8|Disp16|Disp32|Disp32S|BaseIndex|InvMem) /* General memory */
|
||||
/* The following aliases are defined because the opcode table
|
||||
carefully specifies the allowed memory types for each instruction.
|
||||
At the moment we can only tell a memory reference size by the
|
||||
instruction suffix, so there's not much point in defining Mem8,
|
||||
Mem16, Mem32 and Mem64 opcode modifiers - We might as well just use
|
||||
the suffix directly to check memory operands. */
|
||||
#define LLongMem AnyMem /* 64 bits (or more) */
|
||||
#define LongMem AnyMem /* 32 bit memory ref */
|
||||
#define ShortMem AnyMem /* 16 bit memory ref */
|
||||
#define WordMem AnyMem /* 16 or 32 bit memory ref */
|
||||
#define ByteMem AnyMem /* 8 bit memory ref */
|
||||
}
|
||||
template;
|
||||
|
||||
|
@ -389,47 +422,70 @@ template;
|
|||
END.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
const template *start;
|
||||
const template *end;
|
||||
} templates;
|
||||
{
|
||||
const template *start;
|
||||
const template *end;
|
||||
}
|
||||
templates;
|
||||
|
||||
/* these are for register name --> number & type hash lookup */
|
||||
typedef struct
|
||||
{
|
||||
char *reg_name;
|
||||
unsigned int reg_type;
|
||||
unsigned int reg_num;
|
||||
}
|
||||
{
|
||||
char *reg_name;
|
||||
unsigned int reg_type;
|
||||
unsigned int reg_flags;
|
||||
#define RegRex 0x1 /* Extended register. */
|
||||
#define RegRex64 0x2 /* Extended 8 bit register. */
|
||||
unsigned int reg_num;
|
||||
}
|
||||
reg_entry;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
char *seg_name;
|
||||
unsigned int seg_prefix;
|
||||
}
|
||||
{
|
||||
char *seg_name;
|
||||
unsigned int seg_prefix;
|
||||
}
|
||||
seg_entry;
|
||||
|
||||
/* 386 operand encoding bytes: see 386 book for details of this. */
|
||||
/* 386 operand encoding bytes: see 386 book for details of this. */
|
||||
typedef struct
|
||||
{
|
||||
unsigned int regmem; /* codes register or memory operand */
|
||||
unsigned int reg; /* codes register operand (or extended opcode) */
|
||||
unsigned int mode; /* how to interpret regmem & reg */
|
||||
}
|
||||
{
|
||||
unsigned int regmem; /* codes register or memory operand */
|
||||
unsigned int reg; /* codes register operand (or extended opcode) */
|
||||
unsigned int mode; /* how to interpret regmem & reg */
|
||||
}
|
||||
modrm_byte;
|
||||
|
||||
/* 386 opcode byte to code indirect addressing. */
|
||||
/* x86-64 extension prefix. */
|
||||
typedef struct
|
||||
{
|
||||
unsigned base;
|
||||
unsigned index;
|
||||
unsigned scale;
|
||||
unsigned int mode64;
|
||||
unsigned int extX; /* Used to extend modrm reg field. */
|
||||
unsigned int extY; /* Used to extend SIB index field. */
|
||||
unsigned int extZ; /* Used to extend modrm reg/mem, SIB base, modrm base fields. */
|
||||
unsigned int empty; /* Used to old-style byte registers to new style. */
|
||||
}
|
||||
rex_byte;
|
||||
|
||||
/* 386 opcode byte to code indirect addressing. */
|
||||
typedef struct
|
||||
{
|
||||
unsigned base;
|
||||
unsigned index;
|
||||
unsigned scale;
|
||||
}
|
||||
sib_byte;
|
||||
|
||||
/* x86 arch names and features */
|
||||
typedef struct
|
||||
{
|
||||
const char *name; /* arch name */
|
||||
unsigned int flags; /* cpu feature flags */
|
||||
}
|
||||
arch_entry;
|
||||
|
||||
/* The name of the global offset table generated by the compiler. Allow
|
||||
this to be overridden if need be. */
|
||||
this to be overridden if need be. */
|
||||
#ifndef GLOBAL_OFFSET_TABLE_NAME
|
||||
#define GLOBAL_OFFSET_TABLE_NAME "_GLOBAL_OFFSET_TABLE_"
|
||||
#endif
|
||||
|
@ -451,13 +507,12 @@ if ((n) && !need_pass_2 \
|
|||
&& (!(fill) || ((char)*(fill) == (char)0x90 && (len) == 1)) \
|
||||
&& subseg_text_p (now_seg)) \
|
||||
{ \
|
||||
char *p; \
|
||||
p = frag_var (rs_align_code, 15, 1, (relax_substateT) max, \
|
||||
(symbolS *) 0, (offsetT) (n), (char *) 0); \
|
||||
*p = 0x90; \
|
||||
frag_align_code ((n), (max)); \
|
||||
goto around; \
|
||||
}
|
||||
|
||||
#define MAX_MEM_FOR_RS_ALIGN_CODE 15
|
||||
|
||||
extern void i386_align_code PARAMS ((fragS *, int));
|
||||
|
||||
#define HANDLE_ALIGN(fragP) \
|
||||
|
@ -480,5 +535,3 @@ extern void sco_id PARAMS ((void));
|
|||
#endif
|
||||
|
||||
#define DIFF_EXPR_OK /* foo-. gets turned into PC relative relocs */
|
||||
|
||||
/* end of tc-i386.h */
|
||||
|
|
Loading…
Reference in a new issue