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https://github.com/freebsd/freebsd-src
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Use 'saveintr' instead of 'savecrit' or 'eflags' to hold the state returned
by intr_disable(). Requested by: bde
This commit is contained in:
parent
c6390f7ac5
commit
0689bdcc19
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=214347
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@ -113,14 +113,14 @@ static struct savefpu fpu_initialstate;
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void
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fpuinit(void)
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{
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register_t savecrit;
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register_t saveintr;
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u_int mxcsr;
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u_short control;
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/*
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* It is too early for critical_enter() to work on AP.
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*/
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savecrit = intr_disable();
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saveintr = intr_disable();
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stop_emulating();
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fninit();
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control = __INITIAL_FPUCW__;
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@ -137,7 +137,7 @@ fpuinit(void)
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bzero(fpu_initialstate.sv_xmm, sizeof(fpu_initialstate.sv_xmm));
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}
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start_emulating();
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intr_restore(savecrit);
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intr_restore(saveintr);
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}
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/*
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@ -787,14 +787,14 @@ void
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enable_K5_wt_alloc(void)
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{
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u_int64_t msr;
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register_t savecrit;
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register_t saveintr;
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/*
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* Write allocate is supported only on models 1, 2, and 3, with
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* a stepping of 4 or greater.
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*/
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if (((cpu_id & 0xf0) > 0) && ((cpu_id & 0x0f) > 3)) {
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savecrit = intr_disable();
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saveintr = intr_disable();
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msr = rdmsr(0x83); /* HWCR */
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wrmsr(0x83, msr & !(0x10));
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@ -825,7 +825,7 @@ enable_K5_wt_alloc(void)
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msr=rdmsr(0x83);
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wrmsr(0x83, msr|0x10); /* enable write allocate */
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intr_restore(savecrit);
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intr_restore(saveintr);
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}
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}
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@ -128,18 +128,18 @@ perfmon_avail(void)
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int
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perfmon_setup(int pmc, unsigned int control)
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{
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register_t savecrit;
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register_t saveintr;
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if (pmc < 0 || pmc >= NPMC)
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return EINVAL;
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perfmon_inuse |= (1 << pmc);
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control &= ~(PMCF_SYS_FLAGS << 16);
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savecrit = intr_disable();
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saveintr = intr_disable();
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ctl_shadow[pmc] = control;
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writectl(pmc);
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wrmsr(msr_pmc[pmc], pmc_shadow[pmc] = 0);
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intr_restore(savecrit);
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intr_restore(saveintr);
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return 0;
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}
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@ -174,17 +174,17 @@ perfmon_fini(int pmc)
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int
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perfmon_start(int pmc)
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{
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register_t savecrit;
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register_t saveintr;
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if (pmc < 0 || pmc >= NPMC)
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return EINVAL;
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if (perfmon_inuse & (1 << pmc)) {
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savecrit = intr_disable();
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saveintr = intr_disable();
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ctl_shadow[pmc] |= (PMCF_EN << 16);
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wrmsr(msr_pmc[pmc], pmc_shadow[pmc]);
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writectl(pmc);
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intr_restore(savecrit);
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intr_restore(saveintr);
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return 0;
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}
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return EBUSY;
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@ -193,17 +193,17 @@ perfmon_start(int pmc)
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int
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perfmon_stop(int pmc)
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{
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register_t savecrit;
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register_t saveintr;
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if (pmc < 0 || pmc >= NPMC)
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return EINVAL;
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if (perfmon_inuse & (1 << pmc)) {
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savecrit = intr_disable();
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saveintr = intr_disable();
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pmc_shadow[pmc] = rdmsr(msr_pmc[pmc]) & 0xffffffffffULL;
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ctl_shadow[pmc] &= ~(PMCF_EN << 16);
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writectl(pmc);
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intr_restore(savecrit);
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intr_restore(saveintr);
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return 0;
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}
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return EBUSY;
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@ -343,7 +343,7 @@ void
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npxinit(void)
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{
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static union savefpu dummy;
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register_t savecrit;
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register_t saveintr;
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u_short control;
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if (!hw_float)
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@ -355,7 +355,7 @@ npxinit(void)
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*
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* It is too early for critical_enter() to work on AP.
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*/
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savecrit = intr_disable();
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saveintr = intr_disable();
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npxsave(&dummy);
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stop_emulating();
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#ifdef CPU_ENABLE_SSE
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@ -366,7 +366,7 @@ npxinit(void)
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control = __INITIAL_NPXCW__;
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fldcw(control);
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start_emulating();
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intr_restore(savecrit);
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intr_restore(saveintr);
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}
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/*
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@ -341,12 +341,12 @@ lapic_setup(int boot)
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{
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struct lapic *la;
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u_int32_t maxlvt;
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register_t eflags;
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register_t saveintr;
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char buf[MAXCOMLEN + 1];
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la = &lapics[lapic_id()];
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KASSERT(la->la_present, ("missing APIC structure"));
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eflags = intr_disable();
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saveintr = intr_disable();
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maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT;
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/* Initialize the TPR to allow all interrupts. */
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@ -393,7 +393,7 @@ lapic_setup(int boot)
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if (maxlvt >= LVT_CMCI)
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lapic->lvt_cmci = lvt_mode(la, LVT_CMCI, lapic->lvt_cmci);
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intr_restore(eflags);
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intr_restore(saveintr);
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}
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void
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@ -1415,7 +1415,7 @@ lapic_ipi_wait(int delay)
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void
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lapic_ipi_raw(register_t icrlo, u_int dest)
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{
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register_t value, eflags;
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register_t value, saveintr;
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/* XXX: Need more sanity checking of icrlo? */
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KASSERT(lapic != NULL, ("%s called too early", __func__));
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@ -1425,7 +1425,7 @@ lapic_ipi_raw(register_t icrlo, u_int dest)
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("%s: reserved bits set in ICR LO register", __func__));
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/* Set destination in ICR HI register if it is being used. */
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eflags = intr_disable();
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saveintr = intr_disable();
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if ((icrlo & APIC_DEST_MASK) == APIC_DEST_DESTFLD) {
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value = lapic->icr_hi;
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value &= ~APIC_ID_MASK;
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@ -1438,7 +1438,7 @@ lapic_ipi_raw(register_t icrlo, u_int dest)
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value &= APIC_ICRLO_RESV_MASK;
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value |= icrlo;
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lapic->icr_lo = value;
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intr_restore(eflags);
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intr_restore(saveintr);
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}
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#define BEFORE_SPIN 1000000
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