Roll minor version. Add ISPASYNC_FW_RESTARTED async event. Add

DEFAULT_FRAMESIZE && DEFAULT_EXEC_THROTTLE references.

MFC after:	1 week
This commit is contained in:
Matt Jacob 2002-06-16 04:52:53 +00:00
parent 9a81395d08
commit 0499ae008f
Notes: svn2git 2020-12-20 02:59:44 +00:00
svn path=/head/; revision=98281

View file

@ -54,7 +54,7 @@
#endif
#define ISP_CORE_VERSION_MAJOR 2
#define ISP_CORE_VERSION_MINOR 6
#define ISP_CORE_VERSION_MINOR 7
/*
* Vector for bus specific code to provide specific services.
@ -287,10 +287,11 @@ typedef struct {
struct lportdb {
u_int32_t
port_type : 8,
: 4,
fc4_type : 4,
loopid : 8,
fc4_type : 4,
last_fabric_dev : 1,
: 2,
relogin : 1,
force_logout : 1,
was_fabric_dev : 1,
fabric_dev : 1,
@ -458,6 +459,9 @@ typedef struct ispsoftc {
#define ISP_CFG_LPORT_ONLY 0x0C /* insist on {N/F}L-Port connection */
#define ISP_CFG_OWNWWPN 0x100 /* override NVRAM wwpn */
#define ISP_CFG_OWNWWNN 0x200 /* override NVRAM wwnn */
#define ISP_CFG_OWNFSZ 0x400 /* override NVRAM frame size */
#define ISP_CFG_OWNLOOPID 0x800 /* override NVRAM loopid */
#define ISP_CFG_OWNEXCTHROTTLE 0x1000 /* override NVRAM execution throttle */
/*
* Prior to calling isp_reset for the first time, the outer layer
@ -723,7 +727,8 @@ typedef enum {
ISPASYNC_TARGET_ACTION, /* other target command action */
ISPASYNC_CONF_CHANGE, /* Platform Configuration Change */
ISPASYNC_UNHANDLED_RESPONSE, /* Unhandled Response Entry */
ISPASYNC_FW_CRASH /* Firmware has crashed */
ISPASYNC_FW_CRASH, /* Firmware has crashed */
ISPASYNC_FW_RESTARTED /* Firmware has been restarted */
} ispasync_t;
int isp_async(struct ispsoftc *, ispasync_t, void *);
@ -852,6 +857,8 @@ void isp_prt(struct ispsoftc *, int level, const char *, ...);
* DEFAULT_LOOPID(struct ispsoftc *) Default FC Loop ID
* DEFAULT_NODEWWN(struct ispsoftc *) Default Node WWN
* DEFAULT_PORTWWN(struct ispsoftc *) Default Port WWN
* DEFAULT_FRAMESIZE(struct ispsoftc *) Default Frame Size
* DEFAULT_EXEC_THROTTLE(struct ispsoftc *) Default Execution Throttle
* These establish reasonable defaults for each platform.
* These must be available independent of card NVRAM and are
* to be used should NVRAM not be readable.