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Fix TTB set operation for armv7.

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Perform sychronization (by "isb" barrier) after TTB is set.  This
is done to ensure that TLB invalidation always executes after
TTB modification and operates on valid CP15 data (per specification).

Submitted by:	Wojciech Macek <wma@semihalf.com>
Reviewed by:	ian@, cognet@
This commit is contained in:
Ian Lepore 2014-04-04 17:39:05 +00:00
parent 4cd27111b9
commit 028a159090
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=264128
1 changed files with 2 additions and 0 deletions
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2
sys/arm/arm/cpufunc_asm_armv7.S
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@ -71,6 +71,7 @@ ENTRY(armv7_setttb)
orr r0, r0, #PT_ATTR
mcr p15, 0, r0, c2, c0, 0 /* Translation Table Base Register 0 (TTBR0) */
isb
#ifdef SMP
mcr p15, 0, r0, c8, c3, 0 /* invalidate I+D TLBs Inner Shareable*/
#else
@ -273,6 +274,7 @@ ENTRY(armv7_context_switch)
orr r0, r0, #PT_ATTR
mcr p15, 0, r0, c2, c0, 0 /* set the new TTB */
isb
#ifdef SMP
mcr p15, 0, r0, c8, c3, 0 /* and flush the I+D tlbs Inner Sharable */
#else