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Better support for recent Myricom 10GbE NICs
- Update to firmware 1.4.39 for dual-chip NIC (10G-PCIE2-xxx) support, and SFP+ i2c support - Identify newer "B" NICs (10G-PCIEx-8B-x) correctly, rather than mis-identifying them as "A" NICs (cosmetic only) - Identify the IFM_10G_LRM ifmedia type, where applicable. - Identify ifmedia types for SFP+ based NICs - Update copyright Sponsored by: Myricom MFC after: 1 week
This commit is contained in:
Andrew Gallatin
parent
b3747cb7d6
commit
016385508f
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=188736
14021
sys/dev/mxge/eth_z8e.h
14021
sys/dev/mxge/eth_z8e.h
File diff suppressed because it is too large
Load diff
14109
sys/dev/mxge/ethp_z8e.h
14109
sys/dev/mxge/ethp_z8e.h
File diff suppressed because it is too large
Load diff
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@ -1,6 +1,6 @@
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/******************************************************************************
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Copyright (c) 2006-2008, Myricom Inc.
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Copyright (c) 2006-2009, Myricom Inc.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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@ -142,13 +142,29 @@ static void mxge_tick(void *arg);
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static int
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mxge_probe(device_t dev)
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{
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if ((pci_get_vendor(dev) == MXGE_PCI_VENDOR_MYRICOM) &&
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((pci_get_device(dev) == MXGE_PCI_DEVICE_Z8E) ||
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(pci_get_device(dev) == MXGE_PCI_DEVICE_Z8E_9))) {
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device_set_desc(dev, "Myri10G-PCIE-8A");
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return 0;
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}
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return ENXIO;
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int rev;
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if ((pci_get_vendor(dev) == MXGE_PCI_VENDOR_MYRICOM) &&
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((pci_get_device(dev) == MXGE_PCI_DEVICE_Z8E) ||
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(pci_get_device(dev) == MXGE_PCI_DEVICE_Z8E_9))) {
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rev = pci_get_revid(dev);
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switch (rev) {
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case MXGE_PCI_REV_Z8E:
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device_set_desc(dev, "Myri10G-PCIE-8A");
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break;
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case MXGE_PCI_REV_Z8ES:
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device_set_desc(dev, "Myri10G-PCIE-8B");
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break;
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default:
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device_set_desc(dev, "Myri10G-PCIE-8??");
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device_printf(dev, "Unrecognized rev %d NIC\n",
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rev);
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break;
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}
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return 0;
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}
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return ENXIO;
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}
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static void
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@ -2505,18 +2521,25 @@ mxge_tx_done(struct mxge_slice_state *ss, uint32_t mcp_idx)
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}
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}
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static struct mxge_media_type mxge_media_types[] =
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static struct mxge_media_type mxge_xfp_media_types[] =
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{
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{IFM_10G_CX4, 0x7f, "10GBASE-CX4 (module)"},
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{IFM_10G_SR, (1 << 7), "10GBASE-SR"},
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{IFM_10G_LR, (1 << 6), "10GBASE-LR"},
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{0, (1 << 5), "10GBASE-ER"},
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{0, (1 << 4), "10GBASE-LRM"},
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{IFM_10G_LRM, (1 << 4), "10GBASE-LRM"},
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{0, (1 << 3), "10GBASE-SW"},
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{0, (1 << 2), "10GBASE-LW"},
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{0, (1 << 1), "10GBASE-EW"},
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{0, (1 << 0), "Reserved"}
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};
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static struct mxge_media_type mxge_sfp_media_types[] =
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{
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{0, (1 << 0), "Reserved"},
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{IFM_10G_LRM, (1 << 6), "10GBASE-LRM"},
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{IFM_10G_LR, (1 << 5), "10GBASE-LR"},
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{IFM_10G_SR, (1 << 4), "10GBASE-SR"}
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};
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static void
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mxge_set_media(mxge_softc_t *sc, int type)
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@ -2539,8 +2562,11 @@ static void
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mxge_media_probe(mxge_softc_t *sc)
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{
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mxge_cmd_t cmd;
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char *cage_type;
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char *ptr;
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int i, err, ms;
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struct mxge_media_type *mxge_media_types = NULL;
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int i, err, ms, mxge_media_type_entries;
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uint32_t byte;
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sc->need_media_probe = 0;
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@ -2568,16 +2594,38 @@ mxge_media_probe(mxge_softc_t *sc)
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}
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}
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if (*ptr == 'C') {
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/* -C is CX4 */
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mxge_set_media(sc, IFM_10G_CX4);
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return;
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}
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else if (*ptr == 'Q') {
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/* -Q is Quad Ribbon Fiber */
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device_printf(sc->dev, "Quad Ribbon Fiber Media\n");
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/* FreeBSD has no media type for Quad ribbon fiber */
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return;
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}
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if (*ptr != 'R') {
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if (*ptr == 'R') {
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/* -R is XFP */
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mxge_media_types = mxge_xfp_media_types;
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mxge_media_type_entries =
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sizeof (mxge_xfp_media_types) /
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sizeof (mxge_xfp_media_types[0]);
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byte = MXGE_XFP_COMPLIANCE_BYTE;
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cage_type = "XFP";
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}
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if (*ptr == 'S' || *(ptr +1) == 'S') {
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/* -S or -2S is SFP+ */
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mxge_media_types = mxge_sfp_media_types;
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mxge_media_type_entries =
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sizeof (mxge_sfp_media_types) /
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sizeof (mxge_sfp_media_types[0]);
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cage_type = "SFP+";
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byte = 3;
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}
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if (mxge_media_types == NULL) {
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device_printf(sc->dev, "Unknown media type: %c\n", *ptr);
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return;
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}
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@ -2591,52 +2639,52 @@ mxge_media_probe(mxge_softc_t *sc)
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*/
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cmd.data0 = 0; /* just fetch 1 byte, not all 256 */
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cmd.data1 = MXGE_XFP_COMPLIANCE_BYTE; /* the byte we want */
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err = mxge_send_cmd(sc, MXGEFW_CMD_XFP_I2C_READ, &cmd);
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if (err == MXGEFW_CMD_ERROR_XFP_FAILURE) {
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cmd.data1 = byte;
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err = mxge_send_cmd(sc, MXGEFW_CMD_I2C_READ, &cmd);
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if (err == MXGEFW_CMD_ERROR_I2C_FAILURE) {
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device_printf(sc->dev, "failed to read XFP\n");
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}
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if (err == MXGEFW_CMD_ERROR_XFP_ABSENT) {
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device_printf(sc->dev, "Type R with no XFP!?!?\n");
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if (err == MXGEFW_CMD_ERROR_I2C_ABSENT) {
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device_printf(sc->dev, "Type R/S with no XFP!?!?\n");
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}
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if (err != MXGEFW_CMD_OK) {
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return;
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}
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/* now we wait for the data to be cached */
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cmd.data0 = MXGE_XFP_COMPLIANCE_BYTE;
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err = mxge_send_cmd(sc, MXGEFW_CMD_XFP_BYTE, &cmd);
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cmd.data0 = byte;
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err = mxge_send_cmd(sc, MXGEFW_CMD_I2C_BYTE, &cmd);
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for (ms = 0; (err == EBUSY) && (ms < 50); ms++) {
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DELAY(1000);
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cmd.data0 = MXGE_XFP_COMPLIANCE_BYTE;
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err = mxge_send_cmd(sc, MXGEFW_CMD_XFP_BYTE, &cmd);
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cmd.data0 = byte;
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err = mxge_send_cmd(sc, MXGEFW_CMD_I2C_BYTE, &cmd);
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}
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if (err != MXGEFW_CMD_OK) {
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device_printf(sc->dev, "failed to read XFP (%d, %dms)\n",
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err, ms);
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device_printf(sc->dev, "failed to read %s (%d, %dms)\n",
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cage_type, err, ms);
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return;
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}
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if (cmd.data0 == mxge_media_types[0].bitmask) {
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if (mxge_verbose)
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device_printf(sc->dev, "XFP:%s\n",
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device_printf(sc->dev, "%s:%s\n", cage_type,
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mxge_media_types[0].name);
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mxge_set_media(sc, IFM_10G_CX4);
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return;
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}
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for (i = 1;
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i < sizeof (mxge_media_types) / sizeof (mxge_media_types[0]);
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i++) {
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for (i = 1; i < mxge_media_type_entries; i++) {
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if (cmd.data0 & mxge_media_types[i].bitmask) {
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if (mxge_verbose)
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device_printf(sc->dev, "XFP:%s\n",
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device_printf(sc->dev, "%s:%s\n",
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cage_type,
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mxge_media_types[i].name);
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mxge_set_media(sc, mxge_media_types[i].flag);
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return;
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}
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}
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device_printf(sc->dev, "XFP media 0x%x unknown\n", cmd.data0);
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device_printf(sc->dev, "%s media 0x%x unknown\n", cage_type,
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cmd.data0);
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return;
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}
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@ -1,6 +1,6 @@
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/*******************************************************************************
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Copyright (c) 2006-2007, Myricom Inc.
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Copyright (c) 2006-2009, Myricom Inc.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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@ -263,7 +263,10 @@ struct mxge_softc {
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#define MXGE_PCI_VENDOR_MYRICOM 0x14c1
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#define MXGE_PCI_DEVICE_Z8E 0x0008
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#define MXGE_PCI_DEVICE_Z8E_9 0x0009
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#define MXGE_PCI_REV_Z8E 0
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#define MXGE_PCI_REV_Z8ES 1
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#define MXGE_XFP_COMPLIANCE_BYTE 131
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#define MXGE_SFP_COMPLIANCE_BYTE 3
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#define MXGE_HIGHPART_TO_U32(X) \
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(sizeof (X) == 8) ? ((uint32_t)((uint64_t)(X) >> 32)) : (0)
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@ -1,6 +1,6 @@
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/*******************************************************************************
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Copyright (c) 2006-2008, Myricom Inc.
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Copyright (c) 2006-2009, Myricom Inc.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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@ -34,7 +34,7 @@ POSSIBILITY OF SUCH DAMAGE.
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#define MXGEFW_VERSION_MAJOR 1
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#define MXGEFW_VERSION_MINOR 4
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#ifdef MXGEFW
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#if defined MXGEFW && !defined _stdint_h_
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typedef signed char int8_t;
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typedef signed short int16_t;
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typedef signed int int32_t;
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@ -182,63 +182,63 @@ enum myri10ge_mcp_cmd_type {
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MXGEFW_CMD_NONE = 0,
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/* Reset the mcp, it is left in a safe state, waiting
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for the driver to set all its parameters */
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MXGEFW_CMD_RESET,
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MXGEFW_CMD_RESET = 1,
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/* get the version number of the current firmware..
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(may be available in the eeprom strings..? */
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MXGEFW_GET_MCP_VERSION,
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MXGEFW_GET_MCP_VERSION = 2,
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/* Parameters which must be set by the driver before it can
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issue MXGEFW_CMD_ETHERNET_UP. They persist until the next
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MXGEFW_CMD_RESET is issued */
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MXGEFW_CMD_SET_INTRQ_DMA,
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MXGEFW_CMD_SET_INTRQ_DMA = 3,
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/* data0 = LSW of the host address
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* data1 = MSW of the host address
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* data2 = slice number if multiple slices are used
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*/
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MXGEFW_CMD_SET_BIG_BUFFER_SIZE, /* in bytes, power of 2 */
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MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, /* in bytes */
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MXGEFW_CMD_SET_BIG_BUFFER_SIZE = 4, /* in bytes, power of 2 */
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MXGEFW_CMD_SET_SMALL_BUFFER_SIZE = 5, /* in bytes */
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/* Parameters which refer to lanai SRAM addresses where the
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driver must issue PIO writes for various things */
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MXGEFW_CMD_GET_SEND_OFFSET,
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MXGEFW_CMD_GET_SMALL_RX_OFFSET,
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MXGEFW_CMD_GET_BIG_RX_OFFSET,
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MXGEFW_CMD_GET_SEND_OFFSET = 6,
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MXGEFW_CMD_GET_SMALL_RX_OFFSET = 7,
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MXGEFW_CMD_GET_BIG_RX_OFFSET = 8,
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/* data0 = slice number if multiple slices are used */
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MXGEFW_CMD_GET_IRQ_ACK_OFFSET,
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MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET,
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MXGEFW_CMD_GET_IRQ_ACK_OFFSET = 9,
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MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET = 10,
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/* Parameters which refer to rings stored on the MCP,
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and whose size is controlled by the mcp */
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MXGEFW_CMD_GET_SEND_RING_SIZE, /* in bytes */
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MXGEFW_CMD_GET_RX_RING_SIZE, /* in bytes */
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MXGEFW_CMD_GET_SEND_RING_SIZE = 11, /* in bytes */
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MXGEFW_CMD_GET_RX_RING_SIZE = 12, /* in bytes */
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/* Parameters which refer to rings stored in the host,
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and whose size is controlled by the host. Note that
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all must be physically contiguous and must contain
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a power of 2 number of entries. */
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MXGEFW_CMD_SET_INTRQ_SIZE, /* in bytes */
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MXGEFW_CMD_SET_INTRQ_SIZE = 13, /* in bytes */
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#define MXGEFW_CMD_SET_INTRQ_SIZE_FLAG_NO_STRICT_SIZE_CHECK (1 << 31)
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/* command to bring ethernet interface up. Above parameters
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(plus mtu & mac address) must have been exchanged prior
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to issuing this command */
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MXGEFW_CMD_ETHERNET_UP,
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MXGEFW_CMD_ETHERNET_UP = 14,
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/* command to bring ethernet interface down. No further sends
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or receives may be processed until an MXGEFW_CMD_ETHERNET_UP
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is issued, and all interrupt queues must be flushed prior
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to ack'ing this command */
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MXGEFW_CMD_ETHERNET_DOWN,
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MXGEFW_CMD_ETHERNET_DOWN = 15,
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/* commands the driver may issue live, without resetting
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the nic. Note that increasing the mtu "live" should
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|
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@ -246,40 +246,40 @@ enum myri10ge_mcp_cmd_type {
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sufficiently large to handle the new mtu. Decreasing
|
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the mtu live is safe */
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MXGEFW_CMD_SET_MTU,
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MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, /* in microseconds */
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MXGEFW_CMD_SET_STATS_INTERVAL, /* in microseconds */
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MXGEFW_CMD_SET_STATS_DMA_OBSOLETE, /* replaced by SET_STATS_DMA_V2 */
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MXGEFW_CMD_SET_MTU = 16,
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MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET = 17, /* in microseconds */
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MXGEFW_CMD_SET_STATS_INTERVAL = 18, /* in microseconds */
|
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MXGEFW_CMD_SET_STATS_DMA_OBSOLETE = 19, /* replaced by SET_STATS_DMA_V2 */
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|
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MXGEFW_ENABLE_PROMISC,
|
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MXGEFW_DISABLE_PROMISC,
|
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MXGEFW_SET_MAC_ADDRESS,
|
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MXGEFW_ENABLE_PROMISC = 20,
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MXGEFW_DISABLE_PROMISC = 21,
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MXGEFW_SET_MAC_ADDRESS = 22,
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MXGEFW_ENABLE_FLOW_CONTROL,
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MXGEFW_DISABLE_FLOW_CONTROL,
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MXGEFW_ENABLE_FLOW_CONTROL = 23,
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MXGEFW_DISABLE_FLOW_CONTROL = 24,
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|
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/* do a DMA test
|
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data0,data1 = DMA address
|
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data2 = RDMA length (MSH), WDMA length (LSH)
|
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command return data = repetitions (MSH), 0.5-ms ticks (LSH)
|
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*/
|
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MXGEFW_DMA_TEST,
|
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MXGEFW_DMA_TEST = 25,
|
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|
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MXGEFW_ENABLE_ALLMULTI,
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MXGEFW_DISABLE_ALLMULTI,
|
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MXGEFW_ENABLE_ALLMULTI = 26,
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MXGEFW_DISABLE_ALLMULTI = 27,
|
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|
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/* returns MXGEFW_CMD_ERROR_MULTICAST
|
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if there is no room in the cache
|
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data0,MSH(data1) = multicast group address */
|
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MXGEFW_JOIN_MULTICAST_GROUP,
|
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MXGEFW_JOIN_MULTICAST_GROUP = 28,
|
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/* returns MXGEFW_CMD_ERROR_MULTICAST
|
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if the address is not in the cache,
|
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or is equal to FF-FF-FF-FF-FF-FF
|
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data0,MSH(data1) = multicast group address */
|
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MXGEFW_LEAVE_MULTICAST_GROUP,
|
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MXGEFW_LEAVE_ALL_MULTICAST_GROUPS,
|
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MXGEFW_LEAVE_MULTICAST_GROUP = 29,
|
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MXGEFW_LEAVE_ALL_MULTICAST_GROUPS = 30,
|
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|
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MXGEFW_CMD_SET_STATS_DMA_V2,
|
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MXGEFW_CMD_SET_STATS_DMA_V2 = 31,
|
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/* data0, data1 = bus addr,
|
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* data2 = sizeof(struct mcp_irq_data) from driver point of view, allows
|
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* adding new stuff to mcp_irq_data without changing the ABI
|
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|
|
@ -289,14 +289,14 @@ enum myri10ge_mcp_cmd_type {
|
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* (in the upper 16 bits).
|
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*/
|
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MXGEFW_CMD_UNALIGNED_TEST,
|
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MXGEFW_CMD_UNALIGNED_TEST = 32,
|
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/* same than DMA_TEST (same args) but abort with UNALIGNED on unaligned
|
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chipset */
|
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|
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MXGEFW_CMD_UNALIGNED_STATUS,
|
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MXGEFW_CMD_UNALIGNED_STATUS = 33,
|
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/* return data = boolean, true if the chipset is known to be unaligned */
|
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|
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MXGEFW_CMD_ALWAYS_USE_N_BIG_BUFFERS,
|
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MXGEFW_CMD_ALWAYS_USE_N_BIG_BUFFERS = 34,
|
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/* data0 = number of big buffers to use. It must be 0 or a power of 2.
|
||||
* 0 indicates that the NIC consumes as many buffers as they are required
|
||||
* for packet. This is the default behavior.
|
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|
|
@ -306,8 +306,8 @@ enum myri10ge_mcp_cmd_type {
|
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* the NIC to be able to receive maximum-sized packets.
|
||||
*/
|
||||
|
||||
MXGEFW_CMD_GET_MAX_RSS_QUEUES,
|
||||
MXGEFW_CMD_ENABLE_RSS_QUEUES,
|
||||
MXGEFW_CMD_GET_MAX_RSS_QUEUES = 35,
|
||||
MXGEFW_CMD_ENABLE_RSS_QUEUES = 36,
|
||||
/* data0 = number of slices n (0, 1, ..., n-1) to enable
|
||||
* data1 = interrupt mode | use of multiple transmit queues.
|
||||
* 0=share one INTx/MSI.
|
||||
|
|
@ -322,18 +322,18 @@ enum myri10ge_mcp_cmd_type {
|
|||
#define MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE 0x1
|
||||
#define MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES 0x2
|
||||
|
||||
MXGEFW_CMD_GET_RSS_SHARED_INTERRUPT_MASK_OFFSET,
|
||||
MXGEFW_CMD_SET_RSS_SHARED_INTERRUPT_DMA,
|
||||
MXGEFW_CMD_GET_RSS_SHARED_INTERRUPT_MASK_OFFSET = 37,
|
||||
MXGEFW_CMD_SET_RSS_SHARED_INTERRUPT_DMA = 38,
|
||||
/* data0, data1 = bus address lsw, msw */
|
||||
MXGEFW_CMD_GET_RSS_TABLE_OFFSET,
|
||||
MXGEFW_CMD_GET_RSS_TABLE_OFFSET = 39,
|
||||
/* get the offset of the indirection table */
|
||||
MXGEFW_CMD_SET_RSS_TABLE_SIZE,
|
||||
MXGEFW_CMD_SET_RSS_TABLE_SIZE = 40,
|
||||
/* set the size of the indirection table */
|
||||
MXGEFW_CMD_GET_RSS_KEY_OFFSET,
|
||||
MXGEFW_CMD_GET_RSS_KEY_OFFSET = 41,
|
||||
/* get the offset of the secret key */
|
||||
MXGEFW_CMD_RSS_KEY_UPDATED,
|
||||
MXGEFW_CMD_RSS_KEY_UPDATED = 42,
|
||||
/* tell nic that the secret key's been updated */
|
||||
MXGEFW_CMD_SET_RSS_ENABLE,
|
||||
MXGEFW_CMD_SET_RSS_ENABLE = 43,
|
||||
/* data0 = enable/disable rss
|
||||
* 0: disable rss. nic does not distribute receive packets.
|
||||
* 1: enable rss. nic distributes receive packets among queues.
|
||||
|
|
@ -350,7 +350,7 @@ enum myri10ge_mcp_cmd_type {
|
|||
#define MXGEFW_RSS_HASH_TYPE_SRC_DST_PORT 0x5
|
||||
#define MXGEFW_RSS_HASH_TYPE_MAX 0x5
|
||||
|
||||
MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE,
|
||||
MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE = 44,
|
||||
/* Return data = the max. size of the entire headers of a IPv6 TSO packet.
|
||||
* If the header size of a IPv6 TSO packet is larger than the specified
|
||||
* value, then the driver must not use TSO.
|
||||
|
|
@ -359,7 +359,7 @@ enum myri10ge_mcp_cmd_type {
|
|||
* always has enough header buffer to store maximum-sized headers.
|
||||
*/
|
||||
|
||||
MXGEFW_CMD_SET_TSO_MODE,
|
||||
MXGEFW_CMD_SET_TSO_MODE = 45,
|
||||
/* data0 = TSO mode.
|
||||
* 0: Linux/FreeBSD style (NIC default)
|
||||
* 1: NDIS/NetBSD style
|
||||
|
|
@ -367,33 +367,37 @@ enum myri10ge_mcp_cmd_type {
|
|||
#define MXGEFW_TSO_MODE_LINUX 0
|
||||
#define MXGEFW_TSO_MODE_NDIS 1
|
||||
|
||||
MXGEFW_CMD_MDIO_READ,
|
||||
MXGEFW_CMD_MDIO_READ = 46,
|
||||
/* data0 = dev_addr (PMA/PMD or PCS ...), data1 = register/addr */
|
||||
MXGEFW_CMD_MDIO_WRITE,
|
||||
MXGEFW_CMD_MDIO_WRITE = 47,
|
||||
/* data0 = dev_addr, data1 = register/addr, data2 = value */
|
||||
|
||||
MXGEFW_CMD_XFP_I2C_READ,
|
||||
/* Starts to get a fresh copy of one byte or of the whole xfp i2c table, the
|
||||
MXGEFW_CMD_I2C_READ = 48,
|
||||
/* Starts to get a fresh copy of one byte or of the module i2c table, the
|
||||
* obtained data is cached inside the xaui-xfi chip :
|
||||
* data0 : "all" flag : 0 => get one byte, 1=> get 256 bytes,
|
||||
* data1 : if (data0 == 0): index of byte to refresh [ not used otherwise ]
|
||||
* data0 : 0 => get one byte, 1=> get 256 bytes
|
||||
* data1 : If data0 == 0: location to refresh
|
||||
* bit 7:0 register location
|
||||
* bit 8:15 is the i2c slave addr (0 is interpreted as 0xA1)
|
||||
* bit 23:16 is the i2c bus number (for multi-port NICs)
|
||||
* If data0 == 1: unused
|
||||
* The operation might take ~1ms for a single byte or ~65ms when refreshing all 256 bytes
|
||||
* During the i2c operation, MXGEFW_CMD_XFP_I2C_READ or MXGEFW_CMD_XFP_BYTE attempts
|
||||
* During the i2c operation, MXGEFW_CMD_I2C_READ or MXGEFW_CMD_I2C_BYTE attempts
|
||||
* will return MXGEFW_CMD_ERROR_BUSY
|
||||
*/
|
||||
MXGEFW_CMD_XFP_BYTE,
|
||||
MXGEFW_CMD_I2C_BYTE = 49,
|
||||
/* Return the last obtained copy of a given byte in the xfp i2c table
|
||||
* (copy cached during the last relevant MXGEFW_CMD_XFP_I2C_READ)
|
||||
* (copy cached during the last relevant MXGEFW_CMD_I2C_READ)
|
||||
* data0 : index of the desired table entry
|
||||
* Return data = the byte stored at the requested index in the table
|
||||
*/
|
||||
|
||||
MXGEFW_CMD_GET_VPUMP_OFFSET,
|
||||
MXGEFW_CMD_GET_VPUMP_OFFSET = 50,
|
||||
/* Return data = NIC memory offset of mcp_vpump_public_global */
|
||||
MXGEFW_CMD_RESET_VPUMP,
|
||||
MXGEFW_CMD_RESET_VPUMP = 51,
|
||||
/* Resets the VPUMP state */
|
||||
|
||||
MXGEFW_CMD_SET_RSS_MCP_SLOT_TYPE,
|
||||
MXGEFW_CMD_SET_RSS_MCP_SLOT_TYPE = 52,
|
||||
/* data0 = mcp_slot type to use.
|
||||
* 0 = the default 4B mcp_slot
|
||||
* 1 = 8B mcp_slot_8
|
||||
|
|
@ -401,7 +405,7 @@ enum myri10ge_mcp_cmd_type {
|
|||
#define MXGEFW_RSS_MCP_SLOT_TYPE_MIN 0
|
||||
#define MXGEFW_RSS_MCP_SLOT_TYPE_WITH_HASH 1
|
||||
|
||||
MXGEFW_CMD_SET_THROTTLE_FACTOR,
|
||||
MXGEFW_CMD_SET_THROTTLE_FACTOR = 53,
|
||||
/* set the throttle factor for ethp_z8e
|
||||
data0 = throttle_factor
|
||||
throttle_factor = 256 * pcie-raw-speed / tx_speed
|
||||
|
|
@ -417,47 +421,52 @@ enum myri10ge_mcp_cmd_type {
|
|||
with tx_boundary == 4096, max-throttle-factor == 4095 => min-speed == 1Gb/s
|
||||
*/
|
||||
|
||||
MXGEFW_CMD_VPUMP_UP,
|
||||
MXGEFW_CMD_VPUMP_UP = 54,
|
||||
/* Allocates VPump Connection, Send Request and Zero copy buffer address tables */
|
||||
MXGEFW_CMD_GET_VPUMP_CLK,
|
||||
MXGEFW_CMD_GET_VPUMP_CLK = 55,
|
||||
/* Get the lanai clock */
|
||||
|
||||
MXGEFW_CMD_GET_DCA_OFFSET,
|
||||
MXGEFW_CMD_GET_DCA_OFFSET = 56,
|
||||
/* offset of dca control for WDMAs */
|
||||
|
||||
/* VMWare NetQueue commands */
|
||||
MXGEFW_CMD_NETQ_GET_FILTERS_PER_QUEUE,
|
||||
MXGEFW_CMD_NETQ_ADD_FILTER,
|
||||
MXGEFW_CMD_NETQ_GET_FILTERS_PER_QUEUE = 57,
|
||||
MXGEFW_CMD_NETQ_ADD_FILTER = 58,
|
||||
/* data0 = filter_id << 16 | queue << 8 | type */
|
||||
/* data1 = MS4 of MAC Addr */
|
||||
/* data2 = LS2_MAC << 16 | VLAN_tag */
|
||||
MXGEFW_CMD_NETQ_DEL_FILTER,
|
||||
MXGEFW_CMD_NETQ_DEL_FILTER = 59,
|
||||
/* data0 = filter_id */
|
||||
MXGEFW_CMD_NETQ_QUERY1,
|
||||
MXGEFW_CMD_NETQ_QUERY2,
|
||||
MXGEFW_CMD_NETQ_QUERY3,
|
||||
MXGEFW_CMD_NETQ_QUERY4,
|
||||
MXGEFW_CMD_NETQ_QUERY1 = 60,
|
||||
MXGEFW_CMD_NETQ_QUERY2 = 61,
|
||||
MXGEFW_CMD_NETQ_QUERY3 = 62,
|
||||
MXGEFW_CMD_NETQ_QUERY4 = 63,
|
||||
|
||||
MXGEFW_CMD_RELAX_RXBUFFER_ALIGNMENT = 64,
|
||||
/* When set, small receive buffers can cross page boundaries.
|
||||
* Both small and big receive buffers may start at any address.
|
||||
* This option has performance implications, so use with caution.
|
||||
*/
|
||||
};
|
||||
typedef enum myri10ge_mcp_cmd_type myri10ge_mcp_cmd_type_t;
|
||||
|
||||
|
||||
enum myri10ge_mcp_cmd_status {
|
||||
MXGEFW_CMD_OK = 0,
|
||||
MXGEFW_CMD_UNKNOWN,
|
||||
MXGEFW_CMD_ERROR_RANGE,
|
||||
MXGEFW_CMD_ERROR_BUSY,
|
||||
MXGEFW_CMD_ERROR_EMPTY,
|
||||
MXGEFW_CMD_ERROR_CLOSED,
|
||||
MXGEFW_CMD_ERROR_HASH_ERROR,
|
||||
MXGEFW_CMD_ERROR_BAD_PORT,
|
||||
MXGEFW_CMD_ERROR_RESOURCES,
|
||||
MXGEFW_CMD_ERROR_MULTICAST,
|
||||
MXGEFW_CMD_ERROR_UNALIGNED,
|
||||
MXGEFW_CMD_ERROR_NO_MDIO,
|
||||
MXGEFW_CMD_ERROR_XFP_FAILURE,
|
||||
MXGEFW_CMD_ERROR_XFP_ABSENT,
|
||||
MXGEFW_CMD_ERROR_BAD_PCIE_LINK
|
||||
MXGEFW_CMD_UNKNOWN = 1,
|
||||
MXGEFW_CMD_ERROR_RANGE = 2,
|
||||
MXGEFW_CMD_ERROR_BUSY = 3,
|
||||
MXGEFW_CMD_ERROR_EMPTY = 4,
|
||||
MXGEFW_CMD_ERROR_CLOSED = 5,
|
||||
MXGEFW_CMD_ERROR_HASH_ERROR = 6,
|
||||
MXGEFW_CMD_ERROR_BAD_PORT = 7,
|
||||
MXGEFW_CMD_ERROR_RESOURCES = 8,
|
||||
MXGEFW_CMD_ERROR_MULTICAST = 9,
|
||||
MXGEFW_CMD_ERROR_UNALIGNED = 10,
|
||||
MXGEFW_CMD_ERROR_NO_MDIO = 11,
|
||||
MXGEFW_CMD_ERROR_I2C_FAILURE = 12,
|
||||
MXGEFW_CMD_ERROR_I2C_ABSENT = 13,
|
||||
MXGEFW_CMD_ERROR_BAD_PCIE_LINK = 14
|
||||
};
|
||||
typedef enum myri10ge_mcp_cmd_status myri10ge_mcp_cmd_status_t;
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
Loading…
Reference in a new issue