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Complete conversion to bus dma. This driver now works on the alpha.
aicasm_symbol.c: Correct an unaligned access problem. You can't rely on DB to store your data in an aligned fashion.
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2020-12-20 02:59:44 +00:00
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@ -34,7 +34,7 @@
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id: aic7xxx.h,v 1.5 1999/01/14 06:14:15 gibbs Exp $
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* $Id: aic7xxx.h,v 1.6 1999/03/05 23:35:47 gibbs Exp $
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*/
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#ifndef _AIC7XXX_H_
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@ -43,22 +43,31 @@
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#include "ahc.h" /* for NAHC from config */
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#include "opt_aic7xxx.h" /* for config options */
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#include <pci/pcivar.h> /* for pcici_t */
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#include <sys/bus.h> /* For device_t */
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#define AHC_MAXTRANSFER_SIZE 0x00ffffff /* limited by 24bit counter */
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#define AHC_NSEG 32 /* The number of dma segments supported.
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* AHC_NSEG can be maxed out at 256 entries,
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* but the kernel will never need to transfer
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* such a large (1MB) request. To reduce the
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* driver's memory consumption, we reduce the
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* max to 32. 16 would work if all transfers
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* are paged alined since the kernel will only
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* generate at most a 64k transfer, but to
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* handle non-page aligned transfers, you need
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* 17, so we round to the next power of two
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* to make allocating SG space easy and
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* efficient.
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#ifndef MAX
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#define MAX(a,b) (((a) > (b)) ? (a) : (b))
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#endif
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#ifndef MIN
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#define MIN(a,b) (((a) < (b)) ? (a) : (b))
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#endif
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/*
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* The maximum transfer per S/G segment.
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*/
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#define AHC_MAXTRANSFER_SIZE 0x00ffffff /* limited by 24bit counter */
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/*
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* The number of dma segments supported. The current implementation limits
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* us to 255 S/G entries (this may change to be unlimited at some point).
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* To reduce the driver's memory consumption, we further limit the number
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* supported to be sufficient to handle the largest mapping supported by
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* the kernel, MAXPHYS. Assuming the transfer is as fragmented as possible
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* and unaligned, this turns out to be the number of paged sized transfers
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* in MAXPHYS plus an extra element to handle any unaligned residual.
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*/
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#define AHC_NSEG (MIN(btoc(MAXPHYS) + 1, 255))
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#define AHC_SCB_MAX 255 /*
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* Up to 255 SCBs on some types of aic7xxx
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@ -75,10 +84,6 @@
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* wrap point of an 8bit counter.
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*/
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#if defined(__FreeBSD__)
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extern u_long ahc_unit;
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#endif
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struct ahc_dma_seg {
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u_int32_t addr;
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u_int32_t len;
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@ -138,7 +143,6 @@ typedef enum {
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* SRAM, we use the default target
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* settings.
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*/
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AHC_INDIRECT_PAGING = 0x008,
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AHC_SHARED_SRAM = 0x010,
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AHC_LARGE_SEEPROM = 0x020,/* Uses C56_66 not C46 */
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AHC_RESET_BUS_A = 0x040,
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@ -228,30 +232,15 @@ struct hardware_scb {
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struct scb {
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struct hardware_scb *hscb;
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STAILQ_ENTRY(scb) links; /* for chaining */
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SLIST_ENTRY(scb) links; /* for chaining */
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union ccb *ccb; /* the ccb for this cmd */
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scb_flag flags;
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bus_dmamap_t dmamap;
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struct ahc_dma_seg *ahc_dma;/* Pointer to SG segments */
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u_int32_t ahc_dmaphys;/* Phsical address of SG list */
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struct ahc_dma_seg *sg_list;
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bus_addr_t sg_list_phys;
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u_int sg_count;/* How full ahc_dma_seg is */
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};
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struct scb_data {
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struct hardware_scb *hscbs; /* Array of hardware SCBs */
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struct scb *scbarray[AHC_SCB_MAX]; /* Array of kernel SCBs */
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STAILQ_HEAD(, scb) free_scbs; /*
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* Pool of SCBs ready to be assigned
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* commands to execute.
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*/
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u_int8_t numscbs;
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u_int8_t maxhscbs; /* Number of SCBs on the card */
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u_int8_t maxscbs; /*
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* Max SCBs we allocate total including
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* any that will force us to page SCBs
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*/
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};
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/*
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* Connection desciptor for select-in requests in target mode.
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* The first byte is the connecting target, followed by identify
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@ -402,10 +391,45 @@ typedef enum {
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MSG_TYPE_TARGET_MSGIN = 0x04
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} ahc_msg_type;
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struct sg_map_node {
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bus_dmamap_t sg_dmamap;
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bus_addr_t sg_physaddr;
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struct ahc_dma_seg* sg_vaddr;
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SLIST_ENTRY(sg_map_node) links;
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};
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struct scb_data {
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struct hardware_scb *hscbs; /* Array of hardware SCBs */
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struct scb *scbarray; /* Array of kernel SCBs */
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SLIST_HEAD(, scb) free_scbs; /*
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* Pool of SCBs ready to be assigned
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* commands to execute.
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*/
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struct scsi_sense_data *sense; /* Per SCB sense data */
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/*
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* "Bus" addresses of our data structures.
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*/
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bus_dma_tag_t hscb_dmat; /* dmat for our hardware SCB array */
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bus_dmamap_t hscb_dmamap;
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bus_addr_t hscb_busaddr;
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bus_dma_tag_t sense_dmat;
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bus_dmamap_t sense_dmamap;
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bus_addr_t sense_busaddr;
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bus_dma_tag_t sg_dmat; /* dmat for our sg segments */
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SLIST_HEAD(, sg_map_node) sg_maps;
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u_int8_t numscbs;
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u_int8_t maxhscbs; /* Number of SCBs on the card */
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u_int8_t init_level; /*
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* How far we've initialized
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* this structure.
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*/
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};
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struct ahc_softc {
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bus_space_tag_t tag;
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bus_space_handle_t bsh;
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bus_dma_tag_t dmat;
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bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */
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struct scb_data *scb_data;
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/*
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@ -447,14 +471,14 @@ struct ahc_softc {
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/* Command Queues */
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u_int8_t qoutfifonext;
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u_int8_t qinfifonext;
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u_int8_t qoutfifo[256];
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u_int8_t qinfifo[256];
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u_int8_t *qoutfifo;
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u_int8_t *qinfifo;
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/*
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* 256 byte array storing the SCBID of outstanding
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* untagged SCBs indexed by TCL.
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*/
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u_int8_t untagged_scbs[256];
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u_int8_t *untagged_scbs;
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/*
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* Hooks into the XPT.
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@ -482,7 +506,7 @@ struct ahc_softc {
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* PCI error interrupt handler.
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*/
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int unsolicited_ints;
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pcici_t pci_config_id;
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device_t device;
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/*
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* Target incoming command FIFO.
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u_int msgout_index; /* Current index in msgout */
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u_int msgin_index; /* Current index in msgin */
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int regs_res_type;
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int regs_res_id;
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int irq_res_type;
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struct resource *regs;
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struct resource *irq;
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void *ih;
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bus_dma_tag_t parent_dmat;
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bus_dma_tag_t shared_data_dmat;
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bus_dmamap_t shared_data_dmamap;
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bus_addr_t shared_data_busaddr;
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/* Number of enabled target mode device on this card */
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u_int enabled_luns;
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/*
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* "Bus" addresses of our data structures.
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*/
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u_int32_t hscb_busaddr;
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/* Initialization level of this data structure */
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u_int init_level;
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};
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struct full_ahc_softc {
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char *ahc_name(struct ahc_softc *ahc);
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struct ahc_softc *ahc_alloc(int unit, u_int32_t io_base,
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vm_offset_t maddr, ahc_chip chip,
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struct ahc_softc*
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ahc_alloc(device_t dev, struct resource *regs, int regs_type,
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int regs_id, bus_dma_tag_t parent_dmat, ahc_chip chip,
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ahc_feature features, ahc_flag flags,
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struct scb_data *scb_data);
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int ahc_reset(struct ahc_softc *ahc);
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@ -25,7 +25,7 @@
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id: aicasm_symbol.c,v 1.4 1997/09/27 19:37:30 gibbs Exp $
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* $Id: aicasm_symbol.c,v 1.5 1998/09/15 07:24:17 gibbs Exp $
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*/
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DBT data;
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while (symtable->seq(symtable, &key, &data, R_FIRST) == 0) {
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symbol_t *cursym;
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symbol_t *stored_ptr;
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cursym = *(symbol_t **)data.data;
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symbol_delete(cursym);
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memcpy(&stored_ptr, data.data, sizeof(stored_ptr));
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symbol_delete(stored_ptr);
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}
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symtable->close(symtable);
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}
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symtable_get(name)
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char *name;
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{
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symbol_t *stored_ptr;
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DBT key;
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DBT data;
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int retval;
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/* NOTREACHED */
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}
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}
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return (*(symbol_t **)data.data);
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memcpy(&stored_ptr, data.data, sizeof(stored_ptr));
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return (stored_ptr);
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}
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symbol_node_t *
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while (symtable->seq(symtable, &key, &data, flag) == 0) {
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symbol_t *cursym;
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cursym = *(symbol_t **)data.data;
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memcpy(&cursym, data.data, sizeof(cursym));
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switch(cursym->type) {
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case REGISTER:
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case SCBLOC:
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id: aicasm_symbol.c,v 1.4 1997/09/27 19:37:30 gibbs Exp $
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* $Id: aicasm_symbol.c,v 1.5 1998/09/15 07:24:17 gibbs Exp $
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*/
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DBT data;
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while (symtable->seq(symtable, &key, &data, R_FIRST) == 0) {
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symbol_t *cursym;
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symbol_t *stored_ptr;
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cursym = *(symbol_t **)data.data;
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symbol_delete(cursym);
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memcpy(&stored_ptr, data.data, sizeof(stored_ptr));
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symbol_delete(stored_ptr);
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}
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symtable->close(symtable);
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}
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symtable_get(name)
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char *name;
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{
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symbol_t *stored_ptr;
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DBT key;
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DBT data;
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int retval;
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/* NOTREACHED */
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}
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}
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return (*(symbol_t **)data.data);
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memcpy(&stored_ptr, data.data, sizeof(stored_ptr));
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return (stored_ptr);
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}
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symbol_node_t *
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while (symtable->seq(symtable, &key, &data, flag) == 0) {
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symbol_t *cursym;
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cursym = *(symbol_t **)data.data;
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memcpy(&cursym, data.data, sizeof(cursym));
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switch(cursym->type) {
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case REGISTER:
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case SCBLOC:
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